Purpose -The reliability of chip-on-film (COF) packages is fundamentally dependent upon the quality of the eutectic Au-Sn joint formed between the Au bumps on the integrated circuit (IC) device and the Sn-plated Cu inner leads. Therefore, it is essential that an appropriate bonding temperature is achieved during the inner lead bonding (ILB) process. The purpose of this paper is to identify the optimal processing conditions which maximize the reliability of the Au-Sn joints. Design/methodology/approach -The paper commences by performing an experimental investigation to establish the temperature at three specific locations within the COF/ILB system in a typical gang-bonding process. The relationship between the setting temperature of the bonding tool and the temperature of the tool surface is then calibrated using an off-line experimental system. An ANSYS finite element (FE) model is then constructed to simulate the temperature distribution within the COF/ILB system under representative temperature conditions. The validity of the numerical model is confirmed by comparing the simulation results with the experimental temperature measurements. The FE model is then used in a 2 3 factorial design process to evaluate the effect of the principal COF/ILB processing parameters, namely the contact area, the tool temperature and the stage temperature, on the temperature induced at the interface between the Au bumps on the IC chip and the Sn-coated Cu leads on the polyimide film. Findings -The results reveal that the interfacial bonding temperature is determined primarily by the stage temperature. Originality/value -A regression analysis model is applied to the factorial design results to construct a COF/ILB design chart which enables the rapid identification of the stage and tool temperatures required to achieve the minimum feasible eutectic bonding temperature.
Chip-On-Film (COF) packaging is an attractive solution for the direct attachment of chips onto a polyimide (PI) substrate patterned with copper leads. However, despite its many advantages, the eutectic Au-Sn alloy formed in the high temperature bonding process has a number of unsolved reliability issues. Accordingly, the current study performs a series of experiments to investigate the heat dissipation characteristics of the COF process in order to develop a design tool to predict the optimum eutectic bonding parameters. In the experiments, the temperature is measured at three separate positions on the inner lead bonding (ILB) apparatus using a thermocouple wire. The heat transfer characteristics of the bonding tool surface are also measured using a system comprising a PID controller, a solid state relay and a thermocouple extension wire. An finite element (FE) model is then constructed to simulate the temperature distribution within the COF/ILB system under equivalent temperature conditions. The validity FE model is used to construct a design chart which specifies the temperatures of the bonding tool and chip support stage which ensure that the Au-Sn eutectic temperature is achieved at the bump / inner lead interface. The results indicate that the tool temperature should be no lower than 100°C (with a stage temperature of 312°C) and no higher than 300°C (with a stage temperature of 302°C ).
The reliability of Chip-On-Film (COF) packages is fundamentally dependent upon the quality of the thermal performance. The present study commences by performing an experimental investigation to establish the temperature at surface of driver IC within the COF packaging application under electric power conditions. A finite element (FE) model is then constructed to simulate the thermal behavior within the COF packaging application under equivalent power conditions. The validity of the numerical model is confirmed by comparing the simulation results with the experimental temperature measurements. The 2-metal-tape FE model was also developed based on a I-metal-tape model to study the thermal spreading effect within the various thickness of copper lead. The results obtained from the 2-metal-tape model showed that increased thickness of copper lead can provide more efficiency to reduce the temperature at driver IC as the COF application.
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