As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connection which are using in advance package is becoming the important consideration while choosing the package solution for the high-speed devices. In this paper, the electrical perfo%ance of the wire bond technology and bump with RDL technology has been presented. By using the full-wave 3D electromagnetic simulators, the experimental results including the passive parasitic parameter analysis (AC Resistance, Inductance and Capacitance) and scattering parameter analysis will be pnented. Discussions on the rise time, cross talk noise, propagation delay for the IOGbitk signal are also included.
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