Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuromorphic systems from conventional computing systems. The brain has evolved over billions of years to solve difficult engineering problems by using efficient, parallel, low-power computation. The goal of NE is to design systems capable of brain-like computation. Numerous large-scale neuromorphic projects have emerged recently. This interdisciplinary field was listed among the top 10 technology breakthroughs of 2014 by the MIT Technology Review and among the top 10 emerging technologies of 2015 by the World Economic Forum. NE has two-way goals: one, a scientific goal to understand the computational properties of biological neural systems by using models implemented in integrated circuits (ICs); second, an engineering goal to exploit the known properties of biological systems to design and implement efficient devices for engineering applications. Building hardware neural emulators can be extremely useful for simulating large-scale neural models to explain how intelligent behavior arises in the brain. The principal advantages of neuromorphic emulators are that they are highly energy efficient, parallel and distributed, and require a small silicon area. Thus, compared to conventional CPUs, these neuromorphic emulators are beneficial in many engineering applications such as for the porting of deep learning algorithms for various recognitions tasks. In this review article, we describe some of the most significant neuromorphic spiking emulators, compare the different architectures and approaches used by them, illustrate their advantages and drawbacks, and highlight the capabilities that each can deliver to neural modelers. This article focuses on the discussion of large-scale emulators and is a continuation of a previous review of various neural and synapse circuits (Indiveri et al., 2011). We also explore applications where these emulators have been used and discuss some of their promising future applications.

As one of the most important members of the two dimensional chalcogenide family, molybdenum disulphide (MoS2) has played a fundamental role in the advancement of low dimensional electronic, optoelectronic and piezoelectric designs. Here, we demonstrate a new approach to solid state synaptic transistors using two dimensional MoS2 floating gate memories. By using an extended floating gate architecture which allows the device to be operated at near-ideal subthreshold swing of 77 mV/decade over four decades of drain current, we have realised a charge tunneling based synaptic memory with performance comparable to the state of the art in neuromorphic designs. The device successfully demonstrates various features of a biological synapse, including pulsed potentiation and relaxation of channel conductance, as well as spike time dependent plasticity (STDP). Our device returns excellent energy efficiency figures and provides a robust platform based on ultrathin two dimensional nanosheets for future neuromorphic applications.Understanding the complexities in the functioning of the human brain has been one of the foremost challenges in the field of neuroscience. Among the several proposed models, only a few can explain the operation of a human brain and that too for a very limited set of functionalities [1][2][3] . From an electronic point of view, the computational architecture of a brain is vastly different from that of a traditional von Neumann architecture based system [4,5] . This has led to the emergence of neuromorphic computation schemes [6][7][8][9][10] . Current computation follows an architecture where processing and storage of data is handled by separate entities whereas in neuromorphic computation, processing and storage of data is handled by a single element which acts as the electrical analogue of a synapse. Mimicing the functionality and density of synapses in the brain would lead to a massive reduction in energy consumption and immensely enhance computational capabilities like parallel processing. Given the high density of synapses required, traditional silicon based devices which are plagued by power dissipation and short channel effects are rendered unsuitable for scalable neuromorphic applications [11,12] . This makes ultrathin two dimensional materials a perfect candidate for the active element of a synaptic transistor given their immunity to short channel effects and excellent gate coupling at nanometer length scales [12,13] .Biologically, a synapse functions by changing its conductivity based on the sequence of synaptic pulses it receives. This is accomplished by varying the concentration of neurotransmitters or chemical stimulants which control the conductivity of the junction between two neurons [14] . An ideal synaptic transistor must possess the ‡ e-mail:tathagata@iisc.ac.in, arindam@iisc.ac.in twin qualities of being a non-volatile memory while inculcating a learning based mechanism to deduce its conductance from the history of applied inputs [15][16][17][18][19][20][21][22][23][24][25][26][27][28...

In this paper, we present the implementation of two types of Bayesian inference problems to demonstrate the potential of building probabilistic algorithms in hardware using single set of building blocks with the ability to perform these computations in real time. The first implementation, referred to as the BEAST (Bayesian Estimation and Stochastic Tracker), demonstrates a simple problem where an observer uses an underlying Hidden Markov Model (HMM) to track a target in one dimension. In this implementation, sensors make noisy observations of the target position at discrete time steps. The tracker learns the transition model for target movement, and the observation model for the noisy sensors, and uses these to estimate the target position by solving the Bayesian recursive equation online. We show the tracking performance of the system and demonstrate how it can learn the observation model, the transition model, and the external distractor (noise) probability interfering with the observations. In the second implementation, referred to as the Bayesian INference in DAG (BIND), we show how inference can be performed in a Directed Acyclic Graph (DAG) using stochastic circuits. We show how these building blocks can be easily implemented using simple digital logic gates. An advantage of the stochastic electronic implementation is that it is robust to certain types of noise, which may become an issue in integrated circuit (IC) technology with feature sizes in the order of tens of nanometers due to their low noise margin, the effect of high-energy cosmic rays and the low supply voltage. In our framework, the flipping of random individual bits would not affect the system performance because information is encoded in a bit stream.

Articles you may be interested inCharacterization of in situ SiNx thin film grown on AlN/GaN heterostructure by metal-organic chemical vapor deposition Appl. Phys. Lett.Structural, optical, and electrical characterization of gadolinium oxide films deposited by low-pressure metalorganic chemical vapor deposition Structure and morphology of epitaxial PbZrO 3 films grown by metalorganic chemical vapor deposition

We report the growth and characterization of gadolinium oxide films deposited on Si͑100͒ and fused quartz in the temperature range of 450-800°C by a low-pressure metalorganic chemical vapor deposition technique using a ␤-diketonate complex of gadolinium as the precursor. The x-ray diffractometry study of the films reveals that, irrespective of the growth temperature, the films grown on fused quartz (i.e., an amorphous substrate) and silicon (i.e., a single-crystal substrate) comprise the cubic Gd 2 O 3 phase with a (111) texture. However, the films grown on fused quartz at higher temperatures also show the presence of the monoclinic phase of Gd 2 O 3 . The growth of strongly oriented films on fused quartz has been understood on the basis of minimization of the surface energy. The scanning electron microscopy and atomic force microscopy studies reveal that the films grown at or above 525°C are densely packed and grainy. Optical properties of the films, as studied by ultraviolet (UV)-visible spectrophotometry and Fourier transform infrared spectroscopy, are found to depend strongly on the chemical vapor deposition condition. The analyses reveal further that the films grown at or above 500°C are free of heteroatoms, i.e., C, N, and H. The optical band gap of the films is in the range of 5.0-5.4 eV. Electrical characterization was carried out on Al/ Gd 2 O 3 / Si metal-insulator-semiconductor structures by capacitance-voltage ͑C -V͒ and current-voltage analyses. The effective dielectric constant of the films was in the range of 7-23. The bidirectional C -V characteristics show a counterclockwise hysteresis due to the presence of slow interface traps. A minimum leakage current of 4.6ϫ 10 -5 A/cm 2 at the 1-MV/ cm field was demonstrated.

The fabrication of integrated circuits (ICs) employing two-dimensional (2D) materials is a major goal of semiconductor industry for the next decade, as it may allow the extension of the Moore’s law, aids in in-memory computing and enables the fabrication of advanced devices beyond conventional complementary metal-oxide-semiconductor (CMOS) technology. However, most circuital demonstrations so far utilizing 2D materials employ methods such as mechanical exfoliation that are not up-scalable for wafer-level fabrication, and their application could achieve only simple functionalities such as logic gates. Here, we present the fabrication of a crossbar array of memristors using multilayer hexagonal boron nitride (h-BN) as dielectric, that exhibit analog bipolar resistive switching in >96% of devices, which is ideal for the implementation of multi-state memory element in most of the neural networks, edge computing and machine learning applications. Instead of only using this memristive crossbar array to solve a simple logical problem, here we go a step beyond and present the combination of this h-BN crossbar array with CMOS circuitry to implement extreme learning machine (ELM) algorithm. The CMOS circuit is used to design the encoder unit, and a h-BN crossbar array of 2D hexagonal boron nitride (h-BN) based memristors is used to implement the decoder functionality. The proposed hybrid architecture is demonstrated for complex audio, image, and other non-linear classification tasks on real-time datasets.

This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

We present a hardware architecture that uses the neural engineering framework (NEF) to implement large-scale neural networks on field programmable gate arrays (FPGAs) for performing massively parallel real-time pattern recognition. NEF is a framework that is capable of synthesising large-scale cognitive systems from subnetworks and we have previously presented an FPGA implementation of the NEF that successfully performs nonlinear mathematical computations. That work was developed based on a compact digital neural core, which consists of 64 neurons that are instantiated by a single physical neuron using a time-multiplexing approach. We have now scaled this approach up to build a pattern recognition system by combining identical neural cores together. As a proof of concept, we have developed a handwritten digit recognition system using the MNIST database and achieved a recognition rate of 96.55%. The system is implemented on a state-of-the-art FPGA and can process 5.12 million digits per second. The architecture and hardware optimisations presented offer high-speed and resource-efficient means for performing high-speed, neuromorphic, and massively parallel pattern recognition and classification tasks.