A 0.3V 10-bit rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC) is realized in 0.18-μm CMOS process. While the supply is 0.3V, a doubleboosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. To lower the power, differential dynamic switches are used to control the splitting capacitors of the digital-to-analog converter. This ADC achieves the SNDR of 54.57dB and the SFDR of 69.89dB, respectively. The power consumes 15.9nW at 5kS/s from a 0.3V supply. A figure-of-merit of 7.3fJ/conversion-step for this ADC is achieved.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.