A W-band frequency generation for FMCW radar application is presented. It cascades a ring based five-push multiplier and a push-push injection-locked oscillator for 10 times multiplication with a two stage power amplifier. The chip is fabricated in 65 nm CMOS technology and its size including ESD-protected pads is . Phase noise of the output signal is 110 dBc/Hz at 1 MHz offset using the 7.8 GHz reference frequency with the phase noise of 132 dBc/Hz at 1 MHz offset. The output power of the complete circuit is larger than 8.8 dBm for the entire output locking range, and -push technique enables unwanted spur suppression larger than 59 dBc. The total power consumption is 265 mW.
이다.Abstract This paper presents a bandpass wireless 3-D chip to chip interface technique. The proposed technique uses direct amplitude modulation of the free running oscillator which especially utilizes the coupling capacitance between two stacked chips as a part of the resonator. Therefore, the oscillator is three dimensionally configured and a simple envelope detector can be used as a receiver without any additional matching circuitry. The proposed link was designed and fabricated using 110 nm CMOS technology and experimental results successfully showed the data transmission at a data rate of 2 Gb/s for the stacked chips with a thickness of 50 μm consuming 4.32 mW. The sizes of the Tx and Rx chips are 0.045 mm 2 and 0.029 mm 2 , respectively.
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