An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is a ected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing e ects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly de ned to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing e ects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach.
Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap between the processor and main memory. However, its use in multitasking computer systems introduces additional preemption delay due to reloading of memory blocks that were replaced during preemption. This cache-related preemption delay poses a serious problem in real-time computing systems where predictability is of utmost importance. In this paper, we propose an enhanced technique for analyzing and thus, bounding the cache-related preemption delay in xed-priority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache-related preemption delay. Second, the technique considers phasing of tasks to eliminate many infeasible task interactions. These two features are expressed as constraints of a linear programming problem whose solution gives a guaranteed upper bound on the cache-related preemption delay. This paper also compares the proposed technique with previous techniques. The results show that the proposed technique gives up to 60% tighter prediction of the worst case response time than the previous techniques.
Airtime fairness, or time-based fairness, has been well recognized as a method to solve WiFi performance anomalies and provide a balance between fairness and spectrum efficiency in multi-rate wireless networks. However, the definition of airtime is vague and simplistic. In this paper, it is demonstrated that current airtime fair scheduling results in unfairness in reality because overheads are neglected or unfairly counted. We introduce a notion of responsible airtime, which covers not only the data transmission time, but also all overheads, even a TCP ACK segment in TCP traffic. An approach based on responsible airtime can provide true time-based fairness, but responsible airtime is too complicated to directly handle. A practical method is thus introduced for evaluating responsible airtime fairness indirectly via throughput measurement. The key element, throughput fair share, of a node, is based on the baseline property in time-based fairness. For each node, an achieving ratio of actual throughput to the throughput fair share is determined, and a new fairness index considering deficiency as well as equity is applied. To validate the feasibility of responsible airtime fairness, we have developed a simple responsible airtime fair scheduler in access points for download traffic. Extensive simulation experiments are conducted in various network and traffic environments using the ns3 simulator. The results show that true time-based fairness is achievable in practice.
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