Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap between the processor and main memory. However, its use in multitasking computer systems introduces additional preemption delay due to reloading of memory blocks that were replaced during preemption. This cache-related preemption delay poses a serious problem in real-time computing systems where predictability is of utmost importance. In this paper, we propose an enhanced technique for analyzing and thus, bounding the cache-related preemption delay in xed-priority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache-related preemption delay. Second, the technique considers phasing of tasks to eliminate many infeasible task interactions. These two features are expressed as constraints of a linear programming problem whose solution gives a guaranteed upper bound on the cache-related preemption delay. This paper also compares the proposed technique with previous techniques. The results show that the proposed technique gives up to 60% tighter prediction of the worst case response time than the previous techniques.
This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. The re-engineering of an embedded system is defined as a development task of meeting newly imposed performance requirements after its hardware and software have been fully implemented. The performance requirements may include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization.Inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new realtime throughput requirement specified as a system's period constraint.The solution approach works in two steps. In the first step, it determines bottleneck processes in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance scaling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirements.Since this approach does not modify carefully designed software structures, it helps reduce the reengineering cycle.
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