Abstract-Designing an optimized common-mode suppression filter for a bend in a differential trace pair on a printed circuit board involves determining the geometrical parameters that simultaneously provide a large reduction of conversion noise, a small differential mode reflection coefficient and low overall loss, given hardware and manufacturing constraints. Therefore, a novel constrained multi-objective optimization technique is proposed that relies on intermediate surrogate models of the different cost functions instead of numerically-expensive fullwave simulations, saving CPU-time and memory resources. As a result a 3D Pareto-front is created and then constrained based on hardware limitations, depicting the trade-off between the costs and allowing an easy selection of the most optimal layout geometry.
A technique to efficiently reduce differential-to-common mode conversion occuring at a bend discontinuity in coupled microstrip lines is investigated. Total signal integrity in the interconnect structure has been improved by minimizing the differential reflection coefficient and insertion loss simultaneously. This is achieved by changing the geometry of the microstrip lines via a tapering section to tightly or very tightly coupled ones in the area of the bend. The new design was manufactured, measured, and validated by means of time-domain analysis, providing very satisfactory results.
IntroductionDifferential signaling is a popular way to transmit signals across circuit boards because of its high electromagnetic immunity against conducted and radiated interfering signals [1]. However, when applied, it is important to keep the differentialto-common mode conversion level low, as this phenomenon has a strong influence on the signal integrity [1][2][3][4][5]. The emergence of new technologies, leading to high bit rates, short rise times and small noise margins, makes this requirement even more stringent. Unfortunately, conversion easily occurs, due to signal trace length mismatch [6] or asymmetric discontinuities in the circuit layout, and in particular at a bend of coupled microstrip lines [2,4, 5]. A reduction of the unwanted common-mode noise can be obtained by applying filtering structures [4, 5] or by adding extra compensating capacitance [2].In [5], a new approach was presented to reduce conversion noise caused by a bend discontinuity over a large frequency range (from DC to 6 GHz), while maintaining low reflection and insertion loss. Whereas in [5] the focus was on frequencydomain S-parameters simulations and circuit modeling, here, we investigate the behavior of improved bends in time domain by means of measurements. Such time domain analysis provides valuable signal integrity related data for circuit designers.
Abstract-Electromagnetic compatibility-aware design of microelectronic circuits is a challenging task as it involves fulfilling strict requirements concerning conducted and radiated emission and immunity levels. Therefore, the need for fast and accurate behavioral models predicting, in the early design stage, the circuit performance during emission or immunity tests, arises rapidly. Hence, in this paper, a new harmonic balance surrogate-based technique to create immunity models of a nonlinear analog circuit is proposed, which hide the real netlist, reduce the simulation time and avoid expensive and time-consuming measurements after tape-out, while still providing high accuracy. The resulting immunity model can be easily integrated into a circuit simulator together with additional subcircuits, e.g. board and package models, as such allowing to efficiently reproduce complete immunity test set-ups during the early design stage and without disclosing any intellectual property. The novel method is validated by means of application to an industrial case study, being an automotive voltage regulator, clearly showing the technique's capabilities and practical advantages.
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