InAs is the only binary III-V compound semiconductor that exhibits a natural surface accumulation due to the high density of donor surface states. The Fermi level is pinned at any surface of an InAs wafer, regardless of orientation. It is therefore very likely that an accumulation layer is present at both the top and bottom surface or interface of a thin InAs epilayer with an intermediate bulk-like region between them. Epitaxial layers of InAs sandwiched between two 30 nm thick layers of In 0.8 Al 0.2 As or In 0.52 Al 0.48 As were grown on InP substrates by solid-source molecular beam epitaxy. Their static and dynamic properties were determined by means of gated Hall, resistivity and C-V measurements using a three-layer model to account for interface accumulation as well as the residual bulk-like intermediate region. The InAs/In 0.8 Al 0.2 As heterojunction interface has a significantly lower density of interface states than that of the In 0.52 Al 0.48 As/InAs interface. It is possible to drive such a structure from accumulation through flat band into depletion by means of moderate negative gate voltages. Using similar measurements, the effect of the thickness of the InAs layer as well as the presence or absence of a step-graded buffer on the density of surface states was determined.
Sung Kwon, "High-order distortion control using a computational prediction method for device overlay,"Abstract. As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.
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