Solution for high-order distortion on extreme illumination condition using computational prediction method

Kang, Yongjoon; Ha, Hunhwan; Kim, Jang-Sun; Shin, Ju Hee; Kim, Young Ha; Nam, Young Sun; Choi, Young-Sin; Affentauschegg, Cedric; Heijden, R.W. van der; Rizvi, U.H.; Geh, Bernd; Janda, Eric; Baselmans, Jan; Sanden, Stefan van der; Kwon, Oh-Sung; Ponomarenko, Mariya; Slotboom, Daan

doi:10.1117/12.2086938

Cited by 3 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…OM Overlay accuracy mainly due to the proxy from S/L target to device pattern has long been unresolved problem on device overlay control. The optical imaging sensitivity to the structure and process variation and pitch sensitivity to lens aberration etc., are leading to the solution of device pattern overlay measurement using SEM [2,[5][6][7][8][9][10] . With the high landing energy and efficient BSE collection, overlay measurement from device patterns of SEM AEI has been applied as overlay accuracy compensation.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

SEM ADI on device overlay: the advantages and outcome

Kim

Park

et al. 2023

Metrology, Inspection, and Process Control XXXVII

View full text Add to dashboard Cite

The advanced logic node is continuously shrinking toward sub-nm node and EUV lithography is the one of main drivers to reach better patterning resolution resulting in reduced process steps. Along with this design rule shrink, On Product Overlay (OPO) requirement has been critical to the device yield making the accuracy and stability of optical overlay measurement to become primary concern on the lithography process control. Historically Optical Microscope (OM) ADI overlay was accepted and the standard for control to meet OPO requirements. Along the past years, as OPO budget diminishes with node-to-node, OM overlay required additional supporting reference data to compensate the inherent accuracy problem. Industry adopted the accuracy correction knob with High Voltage SEM (HV-SEM) at post etch, also known as SEM AEI overlay. The SEM AEI overlay measures the error contribution of different process influence and the overlay mark to real device pattern overly bias together. The inaccuracy of OM ADI overlay has been treated as a non-correctable error components till the on-device overlay measurement of HV-SEM after etching was enabled to compensate the delta known as Non-Zero Offset (NZO) or Mis-Reading Correction (MRC). Today the HV-SEM on-device overlay measurement at AEI is widely adopted as one of critical component to meet the OPO requirement enabling scaling for all types of advanced CMOS devices production. The main driver of On-Device-Overlay (ODO) measurement at AEI step is the see-through imaging capability to see all relevant layers through the stack even though the measurement step/time differs on the same wafer of the ADI optical overlay measurement are ranging from few to two-digit days depending on the process complexity. There has been an increasing need for a faster response of overlay measurements to close the overlay control loop and breakdown the device to target error versus the process overly induce component – in other words, to correct in the right step. This leads to the necessity of SEM ADI overlay measurement. With the recent e-Beam evolution of more higher landing energy, probe current and improved Total Measurement Uncertainty (TMU) performance, SEM ADI overlay measurement is enabled and considered to show the performances to meet market requirements on the selected layers of interest. In this paper, we would like to demonstrate the enablement of SEM ADI overlay measurement including the accuracy comparison with OM ADI overlay on the DBO scribe target versus real device pattern measurement performance. With SEM ADI and AEI overlay measurement on the same patterns, we could also demonstrate the error breakdown between optical target to device and from ADI to AEI process induced error which will enable the better correctable methodology to minimize NZO/MRC. In addition, this process contribution to error breakdown could be extended to improve, in the future, the Edge Placement Error (EPE) control.

show abstract

Section: Discussionmentioning

confidence: 99%

“…PPE is prominent on DRAM device where the combination of small sigma Off-Axis Illumination (OAI) is applied. It has been reduced with lens aberration improvement and active feed forward controls but the requirements of residual error correction between S/L target and device have been tighter with node-to-node scaling [8][9][10][11] .…”

Section: Introductionmentioning

confidence: 99%

SEM ADI on device overlay: the advantages and outcome

Kim

Park

et al. 2023

Metrology, Inspection, and Process Control XXXVII

View full text Add to dashboard Cite

show abstract

“…7 At and below the 10-nm node, the total overlay control at singlenanometer level becomes necessary. The range of these optically driven image edge displacements depends on the pattern shapes, 10 imaging conditions, 11 properties of individual scanners, [12][13][14] as well as postexposure patterning processes. 8 Thus, pattern placement errors arise from the pattern layout design and the imaging tool overlay performance.…”

Section: Introductionmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Tyminski

Sakamoto

Palmer

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

View full text Add to dashboard Cite

As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-8 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-10 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

show abstract

High-order distortion control using a computational prediction method for device overlay

Kang

Affentauschegg

Mulkens

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

Self Cite

View full text Add to dashboard Cite

Sung Kwon, "High-order distortion control using a computational prediction method for device overlay,"Abstract. As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.

show abstract

Solution for high-order distortion on extreme illumination condition using computational prediction method

Cited by 3 publications

References 0 publications

SEM ADI on device overlay: the advantages and outcome

SEM ADI on device overlay: the advantages and outcome

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

High-order distortion control using a computational prediction method for device overlay

Contact Info

Product

Resources

About