Drastic efforts have been realized these last years in order to develop complementary organic technology. This is the essential key to produce elementary lowcost circuits for digital and analog applications. Different techniques [1][2][3] are available nowadays to obtain both N-and/or P-type organic devices. Screen printing is one of the most highly awaited low-cost techniques that can be used to produce organic devices and circuits. It has been widely used in P-type organic technologies [4,5]. Now that N-type semiconductors have become much more easily processed, developers are seeking a complete CMOS and lifetime robust technology. Many previous works have reported on a complete solution based on CMOS technology [6][7][8]. Large-area-compatible organic processes have also been demonstrated [9]. Nevertheless some of the technological steps in these latter reports are not fully printed and/or still present some lithography/vacuum deposition steps. We present here a complete fully printed CMOS technology on flexible substrates showing acceptable device performances and digital/analog circuit functionalities, which can lead to more complex designs.Based on our design toolkit we have processed a testchip including single devices, inverters, ring oscillators and simple analog circuits such as current mirrors, differential pairs and cascodes (see Fig. 18.4.7) in order to show the feasibility of our organic CMOS technology.Our organic CMOS top-gate design fabrication is carried out on a 10×10 cm 2 gold-plated 125μm-thick Polyethylene-naphtalate (PEN) substrate. The first step consists of a patterning by laser ablation of source/drain electrodes, which also serves as first level of interconnections, where we attain a 5μm line/space resolution. P-type and N-type semiconductors are then screen printed on the foil and then annealed at a temperature of 100°C in normal atmospheric conditions. The gate dielectric polymer is screen printed above both semiconductors leaving open vias for level interconnections and then annealed. Finally the gate and the second interconnection level are printed with same technique using a conductive silver ink. A final annealing step at 100°C is performed.We have carried out all our measurements in ambient temperature and pressure. In Fig 18.4.1 we show the transfer and output characteristics of both types of devices for the geometry W/L = 2000/20μm. We observe that both types of devices show equivalent levels of ON and OFF state currents. Table 1 (see Fig. 18.4.2) summarizes the important electrical parameters for 2 different transistor geometries. Threshold voltage and saturation mobility for both types of devices have been monitored on the whole set of available transistors to evaluate their respective dispersions. Figure 18.4.3 shows the distributions of N-and P-type threshold voltage and mobility.For digital applications, elementary inverters and ring oscillators have been tested. In Fig. 18.4.4, we present a fully functional inverter (W n =W p =1000μm and L=20μm) and its corresponding 7-st...
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