Local' critical dimension (CD) variations, defined in this paper as those that impact transistor gate lengths within a localized 2.5 mm X 2.5 mm area of a semiconductor device, are of most critical interest to circuit performance, as these errors determine critical path delays. However, these errors are difficult to quantify in the fab and historically have been neglected by the lithography community. We combine an empirically anchored response surface model with a Monte Carlo engine to examine in detail the variation in local CD error across a typical lens field and as a function of various process parameters. This methodology allows for the correct statistical treatment of systematic and random errors, and enables the separation of in-die and die-to-die CD variations (as the former impact yield much more than the latter). We demonstrate that local CD variation defines the space of allowable process errors to a much greater extent than acrosschip linewidth variation (ACLV) or die-to-die variation, and we use the output of the model to establish control limits for tool parameters for a candidate 90-nm-node alternating phase-shift gate process.