Abstract. In recent years more and more security sensitive applications use passive smart devices such as contactless smart cards and RFID tags. Cost constraints imply a small hardware footprint of all components of a smart device. One particular problem of all passive smart devices such as RFID tags and contactless smart cards are the harsh power constraints. On the other hand, active smart devices have to minimize energy consumption. Recently, many lightweight block ciphers have been published. In this paper we present three different architecture of the ultra-lightweight algorithm present and highlight their suitability for both active and passive smart devices. Our implementation results of the serialized architecture require only 1000 GE. To the best of our knowledge this is the smallest hardware implementation of a cryptographic algorithm with a moderate security level.
BackgroundSmart cards are widely in use for authentication, access control, and payment purposes. Their applications range from access control of ski ressorts and soccer stadiums over parking lots to highly secured areas of both company and goverment buildings. MasterCard, Visa, and JCB are currently defining specifications for contact and contactless payments using smart cards in their EMV standards [17,16]. In recent years there has been an increasing trend towards contactless smart cards. In fact, contactless smart cards are a special subset of passive RFID tags [8]. With regards to the terminology of pervasive computing both can be summarised by the term passive smart devices. Even for very sensitive data passive smart devices are used, e.g. Visa payWave card [22], hence, security mechanism play a key role for these applications.Many smart devices, especially commodities, are very cost sensitive. If the volumes are large enough -and this is indicated by the term pervasive-an application specific integrated circuit (ASIC) will nearly always be cheaper than a programmable micro computer. In hardware the price of an ASIC is roughly equivalent to the area in silicon it requires. The area is usually measured in µm 2 , but this value depends on the fabrication technology and the standard cell G. Grimaud and F.-X. Standaert (Eds.): CARDIS
This paper presents an implementation of trusted boot for embedded systems. While in PCs the trusted computing hardware functionality is spread over CPU, memory controller hub (MCH), IO controller hub (ICH) and Trusted Platform Module (TPM), for embedded systems it is desirable to integrate the whole functionality in one system on chip. Our implementation is a two-processor design with LEON3 open source soft cores (SPARC V8 instruction set), coupled over an AHB interface. One of the processors acts as application processor, the other one as 'secure' coprocessor. The application processor is synthesized with a boot ROM as static root of trust for measurement. The 'secure' coprocessor runs TPM frmware and enables the application processor to boot and run different software while sealing corresponding keys and other secrets to the respective software identity (computed as hash value). We evaluate the design in a Virtex5 FPGA with respect to different measures like resource consumption, code sizes and start times. The 'trusted boot' functionality is realised with a boot time increase of around 25% for a Linux system
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