In this paper, we present an investigation into the benefits DUV lithography for the manufacturing of Trench MOSFETs and its impact on device performance. We discuss experimental results for devices with a pitch size down to 0.6μm fabricated with an unconventional implant topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are benchmarked against previously published Trench MOS technologies by de-embedding the parasitic substrate resistance, revealing a record-low specific on-resistance of 5.3mΩ⋅mm 2 at a breakdown voltage of 30V (V gs =10V).
This paper demonstrates, for the first time, that subatmospheric chemical vapour deposition (SACVD) oxide is a good candidate for 45-nm node as Shallow Trench Isolation (STI) gap-fill as well as a mobility enhancement technique for both <100> and <110> channel orientations. Respectively, 11% and 18% drive current enhancement for NMOS and PMOS transistors as well as a 12% ring oscillator speed improvement compared to a conventional High Density Plasma (HDP) process are reported.
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