We have proposed an integrated method to realize MLC PRAM at 45nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation. (Keywords: PRAM, MLC, speed and reference cell)
IntroductionPRAM is considered as one of the most possible candidates to follow NOR, NAND and DRAM due to its better scalability [1]. The wide resistance range also makes it possible to realize its MLC version [2], which will be more attractive in the market due to low cost. In the paper, we have proposed an integrated scheme for MLC PRAM, which enhances write throughput and secures a reliable read operation against resistance drift and temperature change.
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