MLC PRAM with SLC write-speed and robust read scheme

Abstract

We have proposed an integrated method to realize MLC PRAM at 45nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation. (Keywords: PRAM, MLC, speed and reference cell) IntroductionPRAM is considered as one of the most possible candidates to follow NOR, NAND and DRAM due to its better scalability [1]. The wide resistance range also makes it possible to realize its MLC version [2], which will be more attractive in the market due to low cost. In the paper, we have proposed an integrated scheme for MLC PRAM, which enhances write throughput and secures a reliable read operation against resistance drift and temperature change.

Practical nonvolatile multilevel-cell phase change memory

“…Prior work on resistance drift: Reference cell [16] and timeaware sensing [37] errors. These complementary drift error reduction techniques show limited improvement in error rate.…”

Tri-level-cell phase change memory

“…Researchers have proposed several drifttolerant approaches such as error correction schemes [1,22,12,20], data encoding schemes using relative resistance difference [12,22], a reference cell scheme [6], a time-aware drift estimation mechanism [20], and most recently an efficient scrubbing scheme [1]. Among them, we focus on the most recent work by Awasthi et al [1] that studied an architectural mechanism combining a memory scrubbing scheme with a strong error-correction method for lowering soft error rates of 4LC PCM.…”

“…Note that the state "11" was excluded because it has four transition edges, which cannot be mapped into the Gray code, and also because two tri-level cells have one more state than a threebit binary code. Then, the rest of states and edges are mapped into the Gray code graph as shown in Figure 3(c) 6 , which indicates that all one-hop error transitions of the two-ternary-cell states except ones from/to the "11" state are translated to one-hop error transitions of the three-bit binary code. Note that we need a special process for the "11" state because removing the "11" state from the state mapping cannot prevent error transitions to the "11" state.…”

Phase Change Memory: From Devices to Systems

“…By varying the amplitude, pulse width or fall time of the electrical pulse, it is possible to control the size of the amorphous volume within the cell, thereby tuning the effective cell resistance [60]. By varying the amplitude, pulse width or fall time of the electrical pulse, it is possible to control the size of the amorphous volume within the cell, thereby tuning the effective cell resistance [60].…”