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Fusion of multimodal imaging data supports medical experts with ample information for better disease diagnosis and further clinical investigations. Recently, sparse representation (SR)‐based fusion algorithms has been gaining importance for their high performance. Building a compact, discriminative dictionary with reduced computational effort is a major challenge to these algorithms. Addressing this key issue, we propose an adaptive dictionary learning approach for fusion of multimodal medical images. The proposed approach consists of three steps. First, zero informative patches of source images are discarded by variance computation. Second, the structural information of remaining image patches is evaluated using modified spatial frequency (MSF). Finally, a selection rule is employed to separate the useful informative patches of source images for dictionary learning. At the fusion step, batch‐OMP algorithm is utilized to estimate the sparse coefficients. A novel fusion rule which measures the activity level in both spatial domain and transform domain is adopted to reconstruct the fused image with the sparse vectors and trained dictionary. Experimental results of various medical image pairs and clinical data sets reveal that the proposed fusion algorithm gives better visual quality and competes with existing methodologies both visually and quantitatively.

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In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

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