This paper describes an efficient substrate-bias generator (SBG) ,for low-power and high-speed DRAM's. In this SBG. the charge pumping circuit and driving and supply .voltage circuit are newly proposed. The proposed ciieuit has, advantages as .follows. First, the charge pumping circuit doesn't sufer from V, loss and is upplicable to low-voitage DRAM's. Second? the driving aird supply voltage switching circuit can supply stable substrate voltage with. switching the supply voltage of n: I wing . stage. So. it can reduce the power consumption by niaking a stable substrate back bias voltage (VBJ because of' its high.pumping efficiency.
This paper describes a new architecture and schemes for high speed SRAM. It summarized as fol1ows:I)a Folded Bit-Line Architecture(FBLA) to reduce the delay time of bit-line by decreasing the parastic capacitance, to reduce the area. 2) a Double Word-Line Activation(D WLA) technique to increase the data-rate twice and minimize row path delay, and 3) a High speed sensing scheme to decrease the delay time of sense amplrfiel:To veri& above these, a 8kb SRAM was designed using 0 . 6~ technology. it realized a 600Mbyte/s(300Mx8x2) data-rate and the die size is 2.8mm x 0.85mm.
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