A novel substrate-bias generator for low-power and high-speed DRAMs

Abstract

This paper describes an efficient substrate-bias generator (SBG) ,for low-power and high-speed DRAM's. In this SBG. the charge pumping circuit and driving and supply .voltage circuit are newly proposed. The proposed ciieuit has, advantages as .follows. First, the charge pumping circuit doesn't sufer from V, loss and is upplicable to low-voitage DRAM's. Second? the driving aird supply voltage switching circuit can supply stable substrate voltage with. switching the supply voltage of n: I wing . stage. So. it can reduce the power consumption by niaking a stable substrate back bias voltage (VBJ because of' its high.pumping efficiency.

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

“…Using the substrate bias circuit, the threshold voltage can be decreased to increase the operation speed during on-states, while the threshold voltage can be increased to reduce the steady power consumption during off-states. In DRAM, the leakage current [4][5][6] in the cell access transistor, aggravated by the scaling in the supply voltage and the storage cell dimensions, reduces the data retention time. As a result, the refresh time must be shortened, and the power consumption is increased.…”