In this paper, a small-area and high-efficiency single-inductor multiple output (SIMO) boost converter with digital pulse-width modulation (DPWM) is proposed. The DPWM comprises a delay line using interlaced hysteresis delay cells (IHDCs) that occupy a small area while consuming a low power amount. These proposed IHDCs are applied to replace the conventional delay cells of the prior works for both the power and area reductions. Regarding the DC-DC converter, this technique comprises fewer digital blocks in the feedback path compared with the conventional DC-DC converter, and the DPWM architecture uses IHDCs. The purpose of the digital limiter block is to concede some helpful code for the DPWM. The IHDC topology used for delay in DPWM is of the simplest architecture. The high-side power switch gate drivers need individual phases which are generated by phase control. The Complementary Metal Oxide Semiconductor (CMOS)-fabrication process is 55 nm, with a standard supply voltage of 1.8 V and outputs of 2.2 and 2.4 V. The chip area is approximately 170 × 190 µm and its efficiency is 94.4%.
An efficient synchronous active rectifier and Multi Feedback low drop out (LDO) Regulator coupled with a wireless power receiver (WPR) is proposed in this study. An active rectifier with maximum power conversion efficiency (PCE) of 94.2% is proposed to mitigate the reverse leakage current using zero current sensing. Output voltage and current are regulated by multi-feedback LDO regulator, sharing the single path transistor. The proposed chip is fabricated in the 0.18 µm BCD technology having die area of 16.0 mm 2 . A 94.2% power conversion efficiency with the load current of 800 mA is measured for the proposed active rectifier.
This paper presents an active rectifier design with a gate charge recycling technique. Gate switching increases the switching losses of the active rectifier, therefore, as a way to reduce switching losses, the gate charge recycling technique is proposed. The output power of 15 W is achieved to enable rapid charging using the three standards for wireless charging mode, magnetic induction (WPC and PMA), and magnetic resonance (A4WP). Power-sharing is used to lower the amount of power consumed by each standard mode core. In WPC, and PMA mode zero current sensing (ZCS) technique has been used while in the A4WP mode, the digitally controlled delay adjustment (DCDA) technique has been employed. By using a gate charge recycling block, the efficiency has been considerably improved due to the lower power consumption. It aims to increase the overall efficiency by reusing switching loss using the gate charge recycling block, and it has effectiveness by allowing three standard modes to operate with one single chip. The proposed design combines charge-recycling with zero current sensing techniques to improve power efficiency. The layout size is 4.75 µm 2 . The achieved efficiency is 98.6 % in the magnetic induction method (WPC/PMA) at 15 W, and 94.86 % in the magnetic resonance method (A4WP) with an output power level of 15 W. The chip is fabricated in the BCD 0.18 µm CMOS process.INDEX TERMS Active rectifier, deglitch circuit, gate charge recycling, high efficiency, switching loss, wireless power transfer system, zero current sensing.
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