Semiconductor nanowires have potential applications in photovoltaics, batteries, and thermoelectrics. We report a top-down fabrication method that involves the combination of superionic-solid-state-stamping (S4) patterning with metal-assisted-chemical-etching (MacEtch), to produce silicon nanowire arrays with defined geometry and optical properties in a manufacturable fashion. Strong light emission in the entire visible and near infrared wavelength range at room temperature, tunable by etching condition, attributed to surface features, and enhanced by silver surface plasmon, is demonstrated.

We report the fabrication of degenerately doped silicon (Si) nanowires of different aspect ratios using a simple, low-cost and effective technique that involves metal-assisted chemical etching (MacEtch) combined with soft lithography or thermal dewetting metal patterning. We demonstrate sub-micron diameter Si nanowire arrays with aspect ratios as high as 180:1, and present the challenges in producing solid nanowires using MacEtch as the doping level increases in both p- and n-type Si. We report a systematic reduction in the porosity of these nanowires by adjusting the etching solution composition and temperature. We found that the porosity decreases from top to bottom along the axial direction and increases with etching time. With a MacEtch solution that has a high [HF]:[H(2)O(2)] ratio and low temperature, it is possible to form completely solid nanowires with aspect ratios of less than approximately 10:1. However, further etching to produce longer wires renders the top portion of the nanowires porous.

A two-step metal assisted chemical etching technique is used to systematically vary the sidewall roughness of Si nanowires in vertically aligned arrays. The thermal conductivities of nanowire arrays are studied using time domain thermoreflectance and compared to their high-resolution transmission electron microscopy determined roughness. The thermal conductivity of nanowires with small roughness is close to a theoretical prediction based on an upper limit of the mean-free-paths of phonons given by the nanowire diameter. The thermal conductivity of nanowires with large roughness is found to be significantly below this prediction. Raman spectroscopy reveals that nanowires with large roughness also display significant broadening of the one-phonon peak; the broadening correlates well with the reduction in thermal conductivity. The origin of this broadening is not yet understood, as it is inconsistent with phonon confinement models, but could derive from microstructural changes that affect both the optical phonons observed in Raman scattering and the acoustic phonons that are important for heat conduction. V

2929wileyonlinelibrary.com drug delivery, [ 8,9 ] and biosensing [ 10,11 ] are derived from such integration. However, micro-and nanopatterning of PS has remained a challenge due to the inability of standard microfabrication processes (e.g., photolithography, wet and dry etching) to effectively pattern PS. [ 12 ] In this paper, we demonstrate a low-cost, low-stress, ambient and high-throughput chemical nanoimprint approach to patterning smooth 3D curvilinear PS surfaces in a single imprinting operation. As a demonstration of this process, sinusoidal and parabolic surfaces with potential uses as diffraction gratings and concentrators are fabricated to demonstrate potential onchip micro-optical components.Traditional approaches to patterning Si do not extend to PS because of the permeability and reactivity of the latter. During photolithography and micromachining, photoresist, developers, and etchants infi ltrate the pores, leading to contamination of the substrate, poor sidewall control and over-etching and, in general, poor fi delity of pattern transfer. [ 12,13 ] A simple route to bypass these issues is to perform lithography prior to anodization. The patterned photoresist fi lm is used as a mask during the anodization step leading to 2D embedded PS patterns with micron-scale resolution. [ 14 ] Cost-effective wet-etching processes such as KOH cannot selectively etch PS since multi ple crystal facets are exposed. Recipes for dry etching methods must be specifi cally tailored to a particular pore morphology of the PS being etched and high-aspect ratio features are seldom reported. [ 12 ] To circumvent these issues, micro-contact printing (MP), [ 15 ] dry-removal soft-lithography (DWSL), [ 16 ] and direct imprinting of PS (DIPS) [ 17,18 ] methods have been developed to pattern PS. The MP method uses a stamp that blocks diffusion of reactants during anodization of the silicon surface. As a result, it offers few degrees of freedom for 3D patterning and, thus, is limited to fabricating shallow corrugated patterns. The latter two patterning methods exploit the controlled fracturing or collapsing of the brittle porous material to selectively strip or compress PS. While DWSL is restricted to 2D patterning with microscale resolution, DIPS can generate 3D features with sub-100 nm resolution. DIPS relies on the compaction of PS leading to permanent deformation of the substrate and, thus, modifying spatially the porous morphology and the optical Conventional lithographical techniques used for bulk semiconductors produce dramatically poor results when used for micro and mesoporous materials such as porous silicon (PS). In this work, for the fi rst time, a high-throughput, single-step, direct imprinting process for PS not involving plastic deformation or high-temperature processing is reported. Based on the underlying mechanism of metal-assisted chemical etching (MACE), this process uses a pre-patterned polymer stamp coated with a noble metal catalyst to etch PS immersed in an HF-oxidizer mixture. The process not only overcome...

This paper presents a non-lithographic approach to generate wafer-scale single crystal silicon nanowires (SiNWs) with controlled sidewall profile and surface morphology. The approach begins with silver (Ag) thin-film thermal dewetting, gold (Au) deposition and lift-off to generate a large-scale Au mesh on Si substrates. This is followed by metal-assisted chemical etching (MacEtch), where the Au mesh serves as a catalyst to produce arrays of smooth Si nanowires with tunable taper up to 13°. The mean diameter of the thus fabricated SiNWs can be controlled to range from 62 to 300 nm with standard deviations as small as 13.6 nm, and the areal coverage of the wire arrays can be up to 46%. Control of the mean wire diameter is achieved by controlling the pore diameter of the metallic mesh which is, in turn, controlled by adjusting the initial thin-film thickness and deposition rate. To control the wire surface morphology, a post-fabrication roughening step is added to the approach. This step uses Au nanoparticles and slow-rate MacEtch to produce rms surface roughness up to 3.6 nm.