A 640×512 CMOS image sensor with an 8b bit-serial Nyquist rate ADC per 4 pixels achieves 10.5 × 10.5 µm pixel size at 29% fill factor in 0.35 µm CMOS technology. Binary floating point output with measured dynamic range of of 65536 : 1 is achieved by multiple sampling at exponentially increasing exposure times.D. Yang, A. El Gamal, B. Fowler, and H. Tian 1 Dynamic range, defined as the ratio of the largest nonsaturating signal to the standard deviation of the noise under dark conditions, is a critical figure of merit for image sensors.The dynamic range of an image sensor is often not wide enough to capture scenes with both high lights and dark shadows. This is especially the case for CMOS sensors, which, in general, have lower dynamic range than CCDs. Several approaches have been proposed to enhance the dynamic range of a CMOS APS. In [1] dynamic range is enhanced by increasing well capacity one or more times during exposure time. Another approach, which achieves consistently higher SNR, is multiple sampling. Here the scene is imaged several times at different exposure times and the data is combined to construct a high dynamic range image.For this approach to work at reasonable capture times, readout must be performed at speeds much higher than normal APS speeds. In [2] an APS with two column parallel signal chains is presented. The sensor can simultaneously read out two images, one after a short exposure time T and the other after a much longer exposure time, e.g. 32T . Two images, however, may not be sufficient to represent the areas of the scene that are too dark to be captured in the first image and too bright to be captured in the second. It is difficult to extend the scheme to simultaneously capture more than two images, since more column parallel signal chains must be added at considerable area penalty.In this paper we demonstrate, using a 640×512 image sensor with Nyquist rate pixel level ADC implemented in a 0.35µm CMOS technology, how pixel level ADC enables a highly flexible and efficient implementation of multiple sampling. Since pixel values are available to the ADCs at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected without the long readout time of APS. Typically, hundreds of nanoseconds of settling time per row are required for APS readout. In contrast, using pixel level ADC, digital data is read out at fast SRAM speeds.This demonstrates yet another fundamental advantage of pixel level ADC -the ability to programmably widen dynamic range with no loss in SNR.The 640 × 512 sensor employs the MCBS ADC technique described in [3]. Each 2 × 2 block of pixels share a 1-bit comparator/latch pair. The signals required to operate the ADCs are globally generated by off chip DAC and digital control circuitry. The ADC is bit D. Yang, A. El Gamal, B. Fowler, and H. Tian 2 serial and each bit is generated by peforming a set of comparisons between the pixel values and a RAMP signal. The bits are generated independently and ...

Fixed pattern noise (FPN) for a CCD sensor is modeled as a sample of a spatial white noise process. This model is, however, not adequate for characterizing FPN in CMOS sensors, since the readout circuitry of CMOS sensors and CCDs are very different. The paper presents a model for CMOS FPN as the sum of two components: a column and a pixel component. Each component is modeled by a first order isotropic autoregressive random process, and each component is assumed to be uncorrelated with the other. The parameters of the processes characterize each component of the FPN and the correlations between neighboring pixels and neighboring columns for a batch of sensors. We show how to estimate the model parameters from a set of measurements, and report estimates for 64x64 passive pixel sensor (PPS) and active pixel sensor (APS) test structures implemented in a 0.35 micron CMOS process. High spatial correlations between pixel components were measured for the PPS structures, and between the column components in both PPS and APS. The APS pixel components were uncorrelated.

A CMOS 64 × 64 pixel area image sensor chip using Sigma-Delta modulation at each pixel for A/D conversion is described. The image data output is digital. The chip was fabricated using a 1.2µm two layer metal single layer poly n-well CMOS process. Each pixel block consists of a phototransistor and 22 MOS transistors. Test results demonstrate a dynamic range potentially greater than 93dB, a signal to noise ratio (SNR) of up to 61dB, and dissipation of less than 1mW with a 5V power supply.

No abstract

No abstract

The standard method for measuring QE for a CCD sensor is not adequate for CMOS APS since it does not take into consideration the random offset, gain variations, and nonlinearity introduced by the APS readout circuits. The paper presents a new method to accurately estimate QE of an APS. Instead of varying illumination as in the CCD method, illumination is kept constant and the pixel output is continuously observed -sampling at regular intervals. This makes it possible to eliminate random offset. The experiment is repeated multiple times to obtain good estimates of the pixel output mean and variance at each sample time. The sensor response is approximated by a piecewise linear function and using the Poisson statistics of shot noise (which are also used in the CCD method) gain, charge and read noise are estimated for each line segment. This procedure is repeated at no illumination so that dark charge may be estimated and subtracted from the total charge estimates. The method can also be used to estimate readout noise and gain FPN. Results from 64x64 pixel APS test structures implemented in a 0.35 um CMOS process are reported. Using 6 different chips and 16 pixels per chip QE=O.37, gain FPN=2%, dark charge=832e-, and readout noise= 40e-, are estimated.

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADC's can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320 2 2 2 256 sensor using the MCBS ADC is described. The chip measures 4.14 2 2 2 5.16 mm 2. It achieves 10 2 2 2 10 m 2 pixel size at 28% fill factor in 0.35m CMOS technology. Each 2 2 2 2 2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively. Index Terms-Analog-to-digital conversion, cameras, CMOS image sensors, image sensors, mixed analog-digital integrated circuits, pixel-level analog-to-digital converter (ADC), video cameras. I. INTRODUCTION C MOS technology holds out the promise of integrating image sensing and image processing into a single-chip digital camera. Recent papers [1], [2] report on the integration of an active pixel sensor (APS) with an analog-to-digital converter (ADC), color processing, and control on a single CMOS chip. In [1], Loinaz et al. describe a PC-based singlechip digital color camera, which integrates a photogate APS, automatic gain control, an 8-bit full flash ADC, and all the compute-intensive pixel-rate tasks such as color interpolation, color correction, and image statistics computation. Framerate tasks, such as exposure control and white balance, are implemented in software on the host PC. In [2], Smith et al. describe a single-chip CMOS National Television Systems Committee (NTSC) video camera that integrates an APS, a

No abstract