A hybrid active-passive, continuous time (CT) sigma-delta ( ) modulator with a multibit quantizer is presented. The modulator is designed as a fifth-order, dual-loop architecture, allowing for a maximum quantizer delay of half a clock period. By removing the summing block before the quantizer as well as by introducing an active-passive hybrid loop filter, the design achieves high signal-to-noise ratio (SNR) comparable to a fourth-order active design while dissipating power equivalent to a third-order implementation. A data-weighted averaging (DWA) algorithm implemented with analog reference shuffling is utilized to suppress the mismatches in the current-steering digital-to-analog conversion (DAC) with no extra delay introduced between the quantizer and DAC. The chip, manufactured in a 1.8-V, 0.18-µm complementary metal oxide semiconductor (CMOS) process, experimentally achieves 79.5 dB peak SNR, 78 dB peak signal-to-noise-and-distortion ratio (SNDR), and 84-dB dynamic range over a 1-MHz signal bandwidth. The 0.43-mm 2 test chip consumes 9-mW of power when clocked at 128 MHz.
A high-speed low power decimation filter, as a part of a broadband and high resolution sigma-delta AID converter, is implemented in SMIC 130nm IP8M CMOS technology. The decimation filter consists of a comb filter and two half-band filters (HBF). Its power consumption is reduced by adopting poly-phase decomposition technique, multiplierless filter architecture and hardware reusage. With a 500MHz sampling frequency, the decimation filter achieves a signal-to-noise ratio of 63.6dB over 20MHz signal bandwidth, while dissipating 4.8m W and occupying an area of 0.12 mm2•
IntroductionAlong with booming development of integrated circuit technology, wide-band sigma-delta AID converters draw more and more attention in wireless communication for their prominent performance of low power, high resolution and small area. As the key component of sigma-delta AID converters, the decimation filter down-samples high-rate bit-stream and its power should be as low as possible in order to keep the total power of the sigma-delta AID converter low.
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