VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application

Abstract

A high-speed low power decimation filter, as a part of a broadband and high resolution sigma-delta AID converter, is implemented in SMIC 130nm IP8M CMOS technology. The decimation filter consists of a comb filter and two half-band filters (HBF). Its power consumption is reduced by adopting poly-phase decomposition technique, multiplierless filter architecture and hardware reusage. With a 500MHz sampling frequency, the decimation filter achieves a signal-to-noise ratio of 63.6dB over 20MHz signal bandwidth, while dissipating 4.8m W and occupying an area of 0.12 mm2• IntroductionAlong with booming development of integrated circuit technology, wide-band sigma-delta AID converters draw more and more attention in wireless communication for their prominent performance of low power, high resolution and small area. As the key component of sigma-delta AID converters, the decimation filter down-samples high-rate bit-stream and its power should be as low as possible in order to keep the total power of the sigma-delta AID converter low.