Recombination of photo-generated charge carriers at metalsemiconductor junctions is a strong limiting factor in achieving high efficiencies for conventional c-Si solar cells [e.g., aluminum back scatter field, passivated emitter rear contact (PERC), etc.]. [1-3] This can be reduced by squeezing the metallized area fraction, but that results in an increase of fill-factor (FF) loses. A novel approach developed at Fraunhofer ISE, namely, tunnel oxide passivated contacts (TOPCon), attempts to counter this effect by implementing passivating contact structures to drastically reduce metal-semiconductor junction recombination. [1,2,4] Passivated contact layers, such as TOPCon, constitute an ultrathin (1-2 nm) silicon oxide (SiO x) layer grown over the bulk c-Si, which is further deposited upon with a highly doped poly-Si layer and finally capped with SiN x. Together they provide excellent passivation, enabling high implied open circuit voltage (iV oc) [2] and carrier selectivity. [2,4] Furthermore, the depletion zone field generated due to high doping of poly-Si also contributes to the passivation effect. Passivating contacts are, therefore, considered to be the next major technological upgrade in the solar cell technology. [3,4] However, forming metal contacts on TOPCon is still a challenge that requires further investigation and improvements. Some commonly reported concerns pertaining to the conventional screen-printed metallization on TOPCon are 1) higher specific contact resistivity (1.5-10 Ω cm) on thick (>150 nm) poly-Si passivated contacts [5] and 2) increase of metal-induced recombination with decreasing thickness of poly-Si due to the metal spiking through the poly-Si and coming in contact with the bulk c-Si. [6] Spiking of the metal paste through the poly-Si layer drastically increases the J 0,met (recombination current at metal-silicon junction) due to poor shielding of recombination at metal contacts, resulting in a low open circuit voltage (V oc). [6] To prevent the penetration of fire-through metal pastes all the way through to the c-Si substrate, it becomes necessary either to keep the thickness of poly-Si above 120 nm or use low temperature metallization techniques. [7-10] However, a thicker poly-Si layer has two serious drawbacks-increased parasitic absorption and higher cost of ownership (COO). Parasitic absorption inflates with increasing poly-Si thickness, resulting in the loss of short circuit current (J sc), [6,11,12] whereas the COO calculations reveal a jump of around 75% if the poly-Si thickness is increased from 50 to 200 nm. [13] Hence, to keep the parasitic absorption and the cost
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