A design for a large-scale surface code quantum processor based on a node/network approach is introduced for semiconductor quantum dot spin qubits. The minimal node contains only seven quantum dots, and nodes are separated on the micron scale, creating useful space for wiring interconnects and integration of conventional transistor circuits. Entanglement is distributed between neighbouring nodes by loading spin singlets locally and then shuttling one member of the pair through a linear array of empty dots. A node contains one data qubit, two ancilla qubits, and additional dots to facilitate electron shuttling and measurement of the ancillas. A four-node GHZ state is realized by sharing three internode singlets followed by local gate operations and ancilla measurements. Further local operations produce an X or Z stabilizer on the four data qubits, which is the fundamental operation of the surface code. Electron shuttling is simulated in the single-valley case using a simple gate electrode geometry without explicit barrier gates, and demonstrates that adiabatic transport is possible on timescales that do not present a speed bottleneck to the processor. An important shuttling error in a clean system is uncontrolled phase rotation of the spin due to modulation of the electronic g-factor during transport, owing to the Stark effect. This error can be reduced by appropriate electrostatic tuning of the stationary electron's g-factor. arXiv:1807.09941v2 [quant-ph]

Shuttling of single electrons in gate-defined silicon quantum dots is numerically simulated. A minimal gate geometry without explicit tunnel barrier gates is introduced, and used to define a chain of accumulation mode quantum dots, each controlled by a single gate voltage. One-dimensional potentials are derived from a three-dimensional electrostatic model, and used to construct an effective Hamiltonian for efficient simulation. Control pulse sequences are designed by maintaining a fixed adiabaticity, so that different shuttling conditions can be systematically compared. We first use these tools to optimize the device geometry for maximum transport velocity, considering only orbital states and neglecting valley and spin degrees of freedom. Taking realistic geometrical constraints into account, charge shuttling speeds up to ∼ 300 m/s preserve adiabaticity. Coherent spin transport is simulated by including spin-orbit and valley terms in an effective Hamiltonian, shuttling one member of a singlet pair and tracking the entanglement fidelity. With realistic device and material parameters, shuttle speeds in the range 10 − 100 m/s with high spin entanglement fidelities are obtained when the tunneling energy exceeds the Zeeman energy. High fidelity also requires the inter-dot valley phase difference to be below a threshold determined by the ratio of tunneling and Zeeman energies, so that spin-valley-orbit mixing is weak. In this regime, we find that the primary source of infidelity is a coherent spin rotation that is correctable, in principle. The results pertain to proposals for large-scale spin qubit processors in isotopically purified silicon that rely on coherent shuttling of spins to rapidly distribute quantum information between computational nodes.

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