Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.
The current-latched sense amplifier (CLSA) is a promising candidate for detecting stored values in a memory cell. With technology shrinks, however, the input referred offset voltage (V OS ) in the SA increases, resulting in a degradation of the memory read yield. To obtain a high read yield, V OS reduction and cancellation techniques have become essential in deep-submicrometer technology nodes. When determining the V OS in the CLSA, the voltage mismatch of the input NMOS pair is the dominant factor (∼75%), followed by that of the latch NMOS pair (∼25%). In this paper, 1) slow rise time (T RISE ) control technique of SA enable signal and 2) reference voltage (V REF ) biasing technique are proposed, and the effectiveness of the proposed techniques are analyzed for the conventional CLSA with footswitch (FS-CLSA) and offset-canceling CLSA (OC-CLSA). Post-layout based HSPICE simulation results using 28 nm model parameters show that the FS-CLSA with size-up strategy (OC-CLSA) achieves a 17.7% (10.5%) reduction of the standard deviation of V OS (σ OS ) when a slow T RISE of 0.6 ns is employed. The measurement results from a 28 nm test chip show that the OC-CLSA with V REF biasing achieves a 22% reduction of σ OS compared to the conventional OC-CLSA.Index Terms-Current-latched sense amplifier (CLSA), offsetcanceling CLSA (OC-CLSA), offset voltage, read yield, reference voltage (V REF ) biasing, slow rise time (T RISE ) of SA enable signal, threshold voltage (V TH ) mismatch.
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