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High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high level synthesis are two-fold. At first the level of abstraction is raised and secondly this allows for exploring the design space to a higher degree than on register transfer level. The design space can be explored by applying several kinds of source code transformations like loop unrolling and tree height reduction. Performing design space exploration manually leads to inefficient and inflexible mappings. This work describes the automated design space exploration for area timing trade-offs by utilising evolutionary multi-objective optimisation. Several performance improvements for genetic algorithms are introduced, which target a fast and accurate design space exploration. Finally, the performance of the proposed algorithm is evaluated.

This paper presents the setup of a testbed developed for the fast evaluation of RFID systems in two frequency domains. At the one hand the 13.56 MHz and at the other hand the 868 MHz frequency domain are supported. The suggested design flow for configuring the testbed is highly automated and supports rapid evaluations of different designs and implementations within shortest time. Several layers of abstraction for rating existing and future RFID standards are provided, from abstract simulation models down to the implementation on the rapid prototype. This includes a fast setup for measuring and rating existing RFID standards, or running them side by side, as well as the rapid exploration of future RFID designs and various aspects of those prototypes. It allows for verifying both protocol stack-and signal processing of RFID systems. In order to demonstrate this concept, we briefly describe an implemented example system, and our overall hardware layout in detail. Measurement results on two existing RFID standards corroborate the concept.

Complexity demand of modern communication systems, particularly in the wireless domain, grows at an astounding rate, a rate so high that the available complexity and even worse the design productivity required to convert algorithms into silicon are left far behind. This effect is commonly referred to as the design productivity crisis or simply the design gap. Since the design gap is predicted to widen every year, it is of utmost importance to look closer at the design flow of such communication systems in order to find improvements. While various ideas for speeding up designs have been proposed, very few have found their path into existing EDA products. This paper presents requirements for such tools and shows how an open design environment offers a solution to integrate existing EDA tools, allowing for a consistent design flow, considerably speeding up design times

In modern designs for heterogeneous systems with their extreme requirements on power consumption, execution time, silicon area and time-to-market, the HW/SW partitioning problem belongs to the most challenging ones. Usually its formulation, based on task or process graphs with complex communication models, is intractable. Moreover most partitioning problems embed another NP-hard problem in its core: a huge number of valid schedules exist for a single partitioning solution. Powerful heuristics for the partitioning problem rely on list scheduling techniques to solve this scheduling problem. This paper is based on a rescheduling algorithm that performs better than popular list scheduling techniques and still preserves linear complexity by reusing former schedules. A sophisticated communication model is introduced and the rescheduling algorithm is modified to serve multi-core architectures with linear runtime.