Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.
DOI: 10.1109/acssc.2005.1599989
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Fast Rescheduling of Multi-Rate Systems for HW/SW Partitioning Algorithms

Abstract: In modern designs for heterogeneous systems with their extreme requirements on power consumption, execution time, silicon area and time-to-market, the HW/SW partitioning problem belongs to the most challenging ones. Usually its formulation, based on task or process graphs with complex communication models, is intractable. Moreover most partitioning problems embed another NP-hard problem in its core: a huge number of valid schedules exist for a single partitioning solution. Powerful heuristics for the partition… Show more

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Cited by 3 publications
(2 citation statements)
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“…On any DSP, bus, or memory, a simple collision arbitration is applied: earliest job first. More sophisticated schemes have already been evaluated [23], [24], but are not in the scope of this paper.…”
Section: System Partitioningmentioning
confidence: 99%
“…On any DSP, bus, or memory, a simple collision arbitration is applied: earliest job first. More sophisticated schemes have already been evaluated [23], [24], but are not in the scope of this paper.…”
Section: System Partitioningmentioning
confidence: 99%
“…The design space exploration, i.e. architecture selection interacting with hw/sw partitioning [16] and floating-point to fixed-point conversion [4], has decomposed the algorithmic description into a process graph, analysed interprocess communication and flagged the processes to be implemented preferably in either HW or SW. At the backend of this procedure, when the target architecture with one or even more processor cores is the favoured solution, the processor selection starts. At this stage parts of the design, i.e.…”
Section: Introductionmentioning
confidence: 99%