Previous technoloby nodes employing copper interconnects haveshown an abrupt increase in resistance, in excess of the conventional ARIR, = 20% resistance increase for the failure criteria (FC). We have observed a different behavior for 65nm technology electromigration (EM) testing, in which the resistance increase is sloped after the initial step increase in resistance. The resistance step (R-step) increase is less than 20%, so that the sloped region (R-slope) occupies a portion of the 20% FC. We explain the two regions based on the full span void formation (R-step), followed by void growth along the length direction (R-slope). For the first time, we use this sloped region to obtain values for the EM activation energy ((3) and current exponent ( H ) of dual-damascene Cu interconnects, which agree very well with values obtained from the fpilure time associated with the initial resistance step. We also show that the sloped region gives rise to an apparent bimodal distribution, with associated increase in the effective log-normal sigma values, when the usual 20% FC is used. We propose a new FC corresponding to the time of the initial R-step increase, to avoid these drawbacks. The increased importance of the R-slope region (RSR) arises from the partially scaled metal barrier thickness, which allows for increased current shunting in the barrier laycr. These RSR effects will become even more evident in technology nodes beyond 65nm. [Kqvwovds: Electromigration, 65nm technology] IEEE 05CH37616 4YAnnual International Reliability Physics Symposium, San Jose, 2005
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