The contactless electrical characterization techniques MDP and MD‐PICTS will be presented in this paper. Both methods are predestined for defect investigation in a variety of semiconductors. Due to a so far not reached sensitivity, major advantages of MDP are its high spatial resolution and its measurement speed, which allows for two dimensional inline measurements at production speed. Furthermore a versatile numerical tool for simulations of electrical properties of a semiconductor as a function of defect parameters was developed. MD‐PICTS is a contactless temperature dependent measurement which allows the determination of activation energies of trap levels in the material. To demonstrate the abilities of both methods, measurements conducted at different semiconductor materials, e.g. silicon, silicon carbide, gallium arsenide and indium phosphide, will be presented exemplarily.
Single crystal production of silicon for solar cell substrates has relied on the Dash neck technique developed more than 50 years ago. The technique is simple and repeatable and enables truly dislocation free crystal growth. It does have drawbacks, however, including limits on throughput and some structural difficulties. It has long been assumed that dislocation-free growth is not possible by any other method. In the 'quasi-mono' crystal growth technique, one of the key elements is the use of large area single crystal seeds. By melting the seeds at near-equilibrium conditions, it is feasible to avoid the production of dislocations during melting. We will review the dislocation relevant details of the large area seeding process and present best case results for dislocation density, including measured minority carrier lifetimes in excess of 1 ms on p-type material. We will focus on dislocation density exclusive of seed boundaries, but we will also present a potential best-case limit for the technique.
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