Abstract-This paper presents a novel model to detect and correct Single Event Upsets in on-board implementations of the AES algorithm, which is based on Hamming error correcting code. The encrypted satellite data can get corrupted before reaching the ground station due to various faults. One major source of faults is the harsh radiation environment, Therefore any electronic systems used on-board satellites such as processors, memories etc. are very susceptible to faults induced by radiation. Single Even Upset (SEU) faults can occur on-board during encryption due to radiation. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out. Faults in the data can also occur during transmission to the ground station due to noisy transmission channels. In this paper the impact of these faults on the data is discussed and compared for all the five modes of AES. From five modes of AES, CRT mode is selected to encrypt satellite video and image links. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out.Index Terms-Encryption, single even upset, hamming code, fault tolerant.
The encrypted satellite data can get corrupted before reaching the ground station due to various faults. One major source of faults is the harsh radiation environment. Single Even Upset (SEU) faults can occur on-board during encryption due to radiation. This paper presents a novel model to detect and correct Single Event Upsets in on-board implementations of the AES algorithm, which is based on Hamming error correcting code. From five modes of AES, CRT mode seems to be the best mode to encrypt satellite video and image links. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out. In this paper the impact of these faults on the data is discussed and compared for all the five modes of AES. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out.
This paper presents the design and simulation of a low phase noise voltage-controlled oscillator (VCO). The oscillator is based upon the classic LC-tuned negative-resistance topology, with a passive inductor. A fundamental relationship of the channel length of MOS transistors in LC tanks VCO and the phase noise is presented. The proposed VCO in the 0.18µm process is designed which is suitable for system integration in transceiver designs. Using this process, complete pattern VCO is designed in ADS. It operates in the 5.5 GHz frequency range with a 1.8V power supply. The power consumption is 7.592mW. The VCO's phase noise level is-106.4dBc/Hz at 1MHz offset.
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