This study proposed an application of symbolic technique on the characterisation of a ring voltage controlled oscillator (VCO) for optimum performance. Here nullor-based symbolic noise modelling and analysis of the CMOS ring VCO is carried out. Circuit equations are processed through modelling of all the metal-oxide-semiconductor field-effect transistors with their nullor equivalent. The closed-form expressions for the total output noise density and phase noise of VCO are obtained. With this technique, the total output noise density and phase noise calculated are compared with the results obtained from the transistorlevel simulation. From the comparison, it has been observed that the nullor-based modelling and analysis simplifies the noise expression as well as reduces CPU execution time. The performance enhancement of the VCO is carried out using two different optimisation techniques. These are particle swam optimisation and non-dominated sorting genetic algorithm. The results obtained for the optimised VCO are then tested using SPICE. The SPICE result shows a significant improvement in phase noise, power consumption and tuning range for the optimised VCO.
In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.
This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.
This paper presents the design and analysis of a miniaturized, coplanar waveguide-fed ultra-wideband monopole on-chip antenna with band-notch characteristics. By incorporating a “U”-shaped slot in the feedline, a band-notch is realized in the frequency range of 7.9–8.4 GHz to avoid interference from the X-band uplink satellite communication system. The proposed antenna achieved good voltage standing wave ratio (VSWR) characteristics with VSWR value <2 for the frequency range of 2.5–20.1 GHz excluding the band-notched frequencies. The fractional bandwidth and bandwidth ratio are obtained as 156% and 8.04:1, respectively. Dominant factors that affect the center frequency and bandwidth of the notched band are thoroughly investigated. This paper addresses both frequency as well as time domain behavior of the proposed structure. Standard 675 µm thick, high resistive silicon substrate (ρ≥8 kΩ-cm, εr = 11.8, and tan δ = 0.01) is used to design the proposed compact antenna structure with a layout area of 8.5 × 11.5 mm2. Fabrication process steps along with simulated and measured data are presented here. A close analogy between simulated and measured data is observed.
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