Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products. IntroductionAs CMOS technology scales down to 22nm, traditional planar transistor architectures [1-3] have reached a fundamental limit for the required short channel control necessary to continue scaling at the rate dictated by Moore's Law. Recently, novel 3-D Tri-Gate transistors have been proven to be capable of high volume manufacturing for high performance CPU products [4]. This paper reports, for the first time, a leading edge 22nm SoC process technology featuring 3-D Tri-Gate transistors which employs high speed logic transistors, low standby power transistors and highvoltage tolerant transistors simultaneously in a single SoC chip to support a wide range of products, including premium smart phones, tablets, netbooks, embedded systems, wireless communications, and ASIC products.

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The ability to cool and manipulate levitated nanoparticles in vacuum is a promising tool for exploring macroscopic quantum mechanics 1,2 , precision measurements of forces 3 and non-equilibrium thermodynamics 4,5. The extreme isolation afforded by optical levitation offers a low noise, undamped environment that has to date been used to measure zeptonewton forces 3 , radiation pressure shot noise 6 , and to demonstrate centre-of-mass motion cooling 7,8. Ground state cooling, and the creation of macroscopic quantum superpositions, are now within reach, but control of both the centre-of-mass and internal temperature is required. While cooling the centre-of-mass motion to micro Kelvin temperatures has now been achieved, the internal temperature has remained at or above room temperature. Here we realise a nanocryostat by refrigerating levitated Yb 3+ :YLF nanocrystals to 130 K using anti-Stokes fluorescence cooling, while simultaneously use the optical trapping field to align the crystal to maximise cooling.