In this paper, a low yield case relating to a systematic array of failures in a ring pattern due to ADC_PLL failures on low yielding wafers will be studied. A systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical in a wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematically open via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference for a wafer Fab that encounters such an issue.
In this paper, a new FA method was proposed and successfully used in the OTP (one time programmable) memory disturbance failure. The traditional FA method PVC (positive voltage contrast) is employed to detect the failed location, but it failed to find it. The more sensitive method, AFP biased current image was also failed to locate the failed location. The new method uses the light to stimulus the sample, and use AFP to scan and measure the induced current. The abnormal contrast was observed. The EFA was performed to probe the failed location to breakdown. The result show the breakdown voltage is lower than good unit. Further PFA was performed to find the Silicon-related defects, which also confirm the success of this method.
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