Supercapacitors are being increasingly used as energy storage systems. Graphene, with its huge specific surface area, superior mechanical flexibility and outstanding electrical properties, constitutes an ideal candidate for the next...

There is an urgent need to fulfill future energy demands for micro and nanoelectronics. This work outlines a number of important design features for carbon-based microsupercapacitors, which enhance both their performance and integration potential and are critical for complimentary metal oxide semiconductor (CMOS) compatibility. Based on these design features, we present CMOS-compatible, graphene-based microsupercapacitors that can be integrated at the back end of the line of the integrated circuit fabrication. Electrode materials and their interfaces play a crucial role for the device characteristics. As such, different carbon-based materials are discussed and the importance of careful design of current collector/electrode interfaces is emphasized. Electrode adhesion is an important factor to improve device performance and uniformity. Additionally, doping of the electrodes can greatly improve the energy density of the devices. As microsupercapacitors are engineered for targeted applications, device scaling is critically important, and we present the first steps toward general scaling trends. Last, we outline a potential future integration scheme for a complete microsystem on a chip, containing sensors, logic, power generation, power management, and power storage. Such a system would be self-powering.

On-chip micro-supercapacitors (MSCs), integrated with energy harvesters, hold substantial promise for developing self-powered wireless sensor systems. However, MSCs have conventionally been manufactured through techniques incompatible with semiconductor fabrication technology, the most significant bottleneck being the electrode deposition technique. Utilization of spin-coating for electrode deposition has shown potential to deliver several complementary metal−oxide−semiconductor (CMOS)-compatible MSCs on a silicon substrate. Yet, their limited electrochemical performance and yield over the substrate have remained challenges obstructing their subsequent integration. We report a facile surface roughening technique for improving the wafer yield and the electrochemical performance of CMOS-compatible MSCs, specifically for reduced graphene oxide as an electrode material. A 4 nm iron layer is deposited and annealed on the wafer substrate to increase the roughness of the surface. In comparison to standard nonroughened MSCs, the increase in surface roughness leads to a 78% increased electrode thickness, 21% improvement in mass retention, 57% improvement in the uniformity of the spin-coated electrodes, and a high yield of 87% working devices on a 2″ silicon substrate. Furthermore, these improvements directly translate to higher capacitive performance with enhanced rate capability, energy, and power density. This technique brings us one step closer to fully integrable CMOS-compatible MSCs in self-powered systems for on-chip wireless sensor electronics.

Laser-induced graphene (LIG) is a graphenic material synthesized from a polymeric substrate through point-by-point laser pyrolysis. It is a fast and cost-effective technique, and it is ideal for flexible electronics and energy storage devices, such as supercapacitors. However, the miniaturization of the thicknesses of the devices, which is important for these applications, has still not been fully explored. Therefore, this work presents an optimized set of laser conditions to fabricate high-quality LIG microsupercapacitors (MSC) from 60 µm thick polyimide substrates. This is achieved by correlating their structural morphology, material quality, and electrochemical performance. The fabricated devices show a high capacitance of 22.2 mF/cm2 at 0.05 mA/cm2, as well as energy and power densities comparable to those of similar devices that are hybridized with pseudocapacitive elements. The performed structural characterization confirms that the LIG material is composed of high-quality multilayer graphene nanoflakes with good structural continuity and an optimal porosity.

A way to obtain graphene-based materials on a large-scale level is by means of chemical methods for the oxidation of graphite to obtain graphene oxide (GO), in combination with thermal, laser, chemical and electrochemical reduction methods to produce reduced graphene oxide (rGO). Among these methods, thermal and laser-based reduction processes are attractive, due to their fast and low-cost characteristics. In this study, first a modified Hummer’s method was applied to obtain graphite oxide (GrO)/graphene oxide. Subsequently, an electrical furnace, a fusion instrument, a tubular reactor, a heating plate, and a microwave oven were used for the thermal reduction, and UV and CO2 lasers were used for the photothermal and/or photochemical reduction. The chemical and structural characterizations of the fabricated rGO samples were performed by Brunauer–Emmett–Teller (BET), X-ray diffraction (XRD), scanning electron microscope (SEM) and Raman spectroscopy measurements. The analysis and comparison of the results revealed that the strongest feature of the thermal reduction methods is the production of high specific surface area, fundamental for volumetric energy applications such as hydrogen storage, whereas in the case of the laser reduction methods, a highly localized reduction is achieved, ideal for microsupercapacitors in flexible electronics.

One of the biggest applications that are coming with the Internet of Things (IoT) are miniaturized sensor networks that connect wirelessly to each other and the internet. Microsupercapacitors (MSCs) are ideal to power these devices, with large cyclability and lifetime. Porous carbons are the material of choice for these devices, but their morphology and manufacturing are far from optimized. Vertically oriented graphene MSCs have shown great promise due to their high specific surface areas and conductivity. In this work, the growth of vertically aligned carbon nanosheets (CNS) on 2-inch wafers has been studied, and it has been used as active material to manufacture MSC and transmission line model (TLM) wafers. The fabricated CNS MSC devices show a capacitance of 7.4 μF (50.7 μF/cm2, normalized to the area of the electrodes), a five-times increase from previous results obtained by the group.