Aircraft information management system (AIMS) requires a highly reliable backplane bus protocol for the communication between its line replaceable units (LRU) to ensure the safety critical hard real time control system operation. As the time driven protocol is more reliable than the event driven protocols, this backplane bus needs to be implemented with time division control protocol. For that matter, more attention is needed to ensure the synchronization issues between LRlls. This paper addresses the controller implementation for bus interface unit (BIll) for the ARINC 659 backplane bus as an example, which controls all the BIll operations. This controller needs to fetch the commands from the table memory, decode them and then execute them to drive the bus for the BUT operations including message operations and synchronization handling. We have designed the Instruction Set Architecture (ISA) for table commands and implemented three Finite State Machines (FSM) for designing this controller along with some glue logic. First FSM is meant for managing commands, second for managing the BIl) current state for synchronization needs, and the third for controlling the BIlJ operations. The aforesaid design has been modeled by using Verilog, Hardware Descriptive Language (HDL) and implemented in Altera Cyclone II board. Results of Modelsim and Quartus proved the cycle accurate implementation of controller in compliance with ARINC 659 specifications.
Data Transfer on a shared resource for hard real time safety-critical functions is a challenging task and demands extremely high reliability. The data bus is the main shared resource for Integrated Modular Avionics (IMA) inter-cabinet or intra-cabinet communication. The ARINC 659 (Aeronautical Radio, Inc.) is a proven standard for digital data transfer on backplane data bus within an IMA cabinet for commercial transport Aircraft. In this paper the design and implementation of data transfer, data decoding/encoding, data comparison, data validation, sync pulse detection, generation and measurement for ARINC 659 is presented. Hardware Description Language (HDL) Verilog is used to model the Design. Computer-aided Design (CAD) tools such as ModelSim, nLint, Debussy and Quartus are used for simulation, verification and implementation purpose. The results show that this implementation for data transfer and sync pulse operation is fully capable of providing desired interface to the Backplane Data Bus for ARINC 659.
High level of reliability is needed by the backplane bus for the Aircraft Information Management System (AIMS) that can ensure the robust and fault tolerant communication between its Line Replaceable Modules (LRM), which in turns ensures the safety critical hard real time control system operation. As the time driven protocol is more reliable than the event driven protocols, this backplane bus needs to be implemented with time division control protocol. For that matter, more attention is needed to ensure the synchronization issues between LRMs. This paper is the extension of our previous work and addresses Table memory and Controller implementation scheme for the Bus Interface Onit (BIU). The aforesaid system is developed for ARINC 659 backplane bus as an example, which controls all the BIU operations. The table memory introduces the cabin wide harmony by providing the same command sequence for all the LRMs. This command sequence also includes the source and destination addresses that avoids extra load on the backplane bus. The controller needs to fetch the commands from the table memory, decode them and then execute them to drive the bus for the BIU operations including message operations and synchronization handling. We have designed the Instruction Set Architecture (ISA) for table commands and implemented three Finite State Machines (FSM) for designing this controller along with some glue logic. First FSM is meant for managing commands, second for managing the BIU current state for synchronization needs, and the third for controlling the BIU operations. The aforesaid design has been modeled by using Verilog, Hardware Descriptive Language (HDL) and implemented in Altera Cyclone II board. Results of Modelsim and Quartus proved the cycle accurate implementation of controller in compliance with ARINC 659 specifications.
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