The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques and subcarrier allocations. The OFDM modulator and demodulator have inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) respectively. The biggest challenge in IFFT/FFT processor is the computation of imaginary and real values. CORDIC has been proved one of the best rotation algorithms for logarithmic, trigonometric, and complex calculations. The proposed work focuses on the OFDM transceiver hardware chip implementation, in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter and receiver respectively. The coordinate rotation digital computer (CORDIC) algorithm has read-only memory (ROM)-based architecture to store FFT twiddle factors and their angle generators. The address generation unit is required to fetch the data and write the results into the memory in the appropriate sequence. CORDIC provides low memory, delay, and optimized hardware on the field-programmable gate array (FPGA) in comparison to normal FFT architecture for the OFDM system. The comparative performance of the FFT and CORDIC-FFT based OFDM transceiver chip is estimated using FPGA parameters: slices, flip-flops, lookup table (LUTs), frequency, power, and delay. The design is developed using integrated synthesis environment (ISE) Xilinx version 14.7 software, synthesized using very-high-speed integrated circuit hardware description language (VHDL), and tested on Virtex-5 FPGA.
In this paper the interactions of extended waves in a noncommutative modified (2 + 1)-dimensional U(2) sigma model are studied. Using the dressing method, we construct an explicit two-wave solution of the noncommutative field equation. The scattering of these waves and large-time factorization are discussed.
The reliability issues like Negative Bias Temperature Instability and Hot Carrier Injection are major concerns in nanoscale design of MOSFET applications. This necessitates that model with higher accuracy for prediction of these degradations and to calculate the lifetime of the CMOS application circuits. Earlier models available in literature are reported to be accurate but the huge time is consumed in evaluating these effects. Hence, we were motivated to propose extended & new models, which evaluate much faster than the available models. We propose a methodology, which uses these models and simulates the circuit degradation due to the effect of NBTI and HCI in CMOS circuit design, and subsequently predicts the lifetime of the circuit. This tool, which we call as Reliability Analysis Tool (ReAl) uses computational support of MATLAB, whereas utilizing accuracy of SPICE simulation for model building, and integrates both in order to provide the lifetime of the CMOS circuit under consideration. Terms -NBTI (Negative Bias Temperature Instability), HCI (Hot Carrier Injection)
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