Hardware Chip Performance of CORDIC Based OFDM Transceiver for Wireless Communication

Abstract

The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques and subcarrier allocations. The OFDM modulator and demodulator have inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) respectively. The biggest challenge in IFFT/FFT processor is the computation of imaginary and real values. CORDIC has been proved one of the best rotation algorithms for logarithmic, trigonometric, and complex calculations. The proposed work focuses on the OFDM transceiver hardware chip implementation, in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter and receiver respectively. The coordinate rotation digital computer (CORDIC) algorithm has read-only memory (ROM)-based architecture to store FFT twiddle factors and their angle generators. The address generation unit is required to fetch the data and write the results into the memory in the appropriate sequence. CORDIC provides low memory, delay, and optimized hardware on the field-programmable gate array (FPGA) in comparison to normal FFT architecture for the OFDM system. The comparative performance of the FFT and CORDIC-FFT based OFDM transceiver chip is estimated using FPGA parameters: slices, flip-flops, lookup table (LUTs), frequency, power, and delay. The design is developed using integrated synthesis environment (ISE) Xilinx version 14.7 software, synthesized using very-high-speed integrated circuit hardware description language (VHDL), and tested on Virtex-5 FPGA.

Sequential logic circuit gold codes for electronics and communication technologies

“…11 illustrates the output waveform of the gold code simulation. The simulation waveform is taken from the Xilinx ISIM simulator [29 , 30] . The test inputs are given below.…”

A Low-Latency RDP-CORDIC Algorithm for Real-Time Signal Processing of Edge Computing Devices in Smart Grid Cyber-Physical Systems

“…A technique reported in low latency CORDIC algorithm [ 34 ] utilized the binaryto-bipolar recoding (BBR) method to reduce the overall iterations to ( N + 1)/3, with no scale factor compensation. Similar to [ 23 ], the CORDIC algorithms [ 35 , 36 , 37 ] cut down time and memory at the expense of accuracy. The CORDIC II algorithm proposed in [ 38 ] had excellent performance in terms of resource consumption and latency, but its low accuracy held it back.…”

A New Recursive Trigonometric Technique for FPGA-Design Implementation

“…The polynomial approximation has higher accuracy, but it requires more complex multiplications and square operations [ 11 ]. In addition, although CORDIC is a commonly used algorithm to implement trigonometric functions in embedded systems, it still has drawbacks in the actual design [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 ]. For example, even though a high-radix CORDIC such as 4-radix, 16-radix, or hybrid CORDIC can reduce the iteration and simplify the process procedure, its computation of the variable scale factor is very time-consuming [ 17 ].…”