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Since 1994, the University of Minnesota has been undertaking a long overdue restructuring of power electronics and electric machines/drives courses. This restructuring allows digital control to be integrated into first courses, thereby teaching students what they need to learn, making these courses appealing, and providing a seamless continuity to advanced courses. By a concise presentation in just two undergraduate courses, this restructuring motivates students to take related courses in programmable logic controllers, microcontrollers and digital signal processor applications. This ensures a first-rate education that is meaningful in the workplace as well as in graduate education leading to a research and development oriented career. This restructuring has several components to it. Outdated topics that waste time and mislead students are deleted. To integrate control in the first courses, unique approaches are developed to convey information more effectively. In the first course in power electronics, a building block is identified in commonly used power converter topologies in order to unify their analysis. In the field of electric drives, the use of space vectors is introduced on a physical basis to describe operation of ac machines in steady state in the first course, and to discuss their optimum control under dynamic conditions in the advanced course. Appropriate simulation software and software-reconfigurable hardware laboratories using a DSP-based rapid prototyping tool are used to support the analytical discussion.

Rq q-axis rotor voltage. u fed d-axis line side converter reference voltage. u feq q-axis line side converter reference voltage. ω mS Stator frequency. ω S Stator frequency. U S Stator voltage. U ac Grid voltage. U dc DC link voltage. i dc DC link current. i L DC link load current. i Ld d-axis nonlinear load current. i Lq q-axis nonlinear load current. i Ldh d-axis harmonic components of load current. i Lqh q-axis harmonic components of load current. ε Angle between stationary axis and rotor axis. µ Angle between stationary axis and stator flux axis. θ Angle between stationary axis and stator voltage axis.

A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.

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