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This paper introduces a digital controller and a segmented power stage that dynamically change mode of operation to maximize power processing efficiency when highly dynamic loads are supplied. The controller operates as a mixedsignal peak current program mode voltage regulator, where a digital current reference is created and used for the efficiency optimization. The losses of the power stage are minimized by combining two methods. Based on the current reference, in each switching cycle, the optimal number of power switch segments and the gate voltage swing level for power MOSFETS are set through a sequence controller and a gate voltage scaling circuit. A 1.8 V, 5 W, 1 MHz buck converter prototype is built. The results verify the operation of the system and show that on-line optimization raises and flattens the efficiency curve by as much as 18%

This paper introduces a novel low-power digital future, are expected to run at frequencies beyond 10 MHz. In controller for high frequency dc-dc switch-mode power supplies addition, the demonstrated systems do not offer a digital (SNIPS) that is well-suited for integration in power management solution for pulse-frequency modulation (PFM), which at light systems of small handheld devices. The controller operates at loads largely improves SMPS efficiency [3]. programmable constant switching frequencies up to 20 MHz and In this paper we present a new low-power architecture that can change mode of operation to improve the overall SNIPS allows integration of digitally controlled SMPS in the existing efficiency. The key elements of the controller are a high and upcoming handheld devices. The controller, shown in frequency digital pulse-width modulator (DPWM), based on a . . . a segmented ring oscillator, and a signal-race based digital pulseFig. , operates at programmable switchMg frequencies up to frequency modulator (DPFM). The controller is implemented in 20 MHz and can switch between PWM and PFM voltage a standard CMOS 0.18 ,Im process and its operation verified regulationmodes. both through simulations and experiments.

This paper introduces a low power digital PFM controller for multi-output dc-dc converters suitable for integration in modern low-power management systems. It utilizes only one inductor to provide multiple output voltages and has very low power consumption. In addition, its reference voltages and switching frequency can be programmed dynamically. To achieve these characteristics two new key functional blocks are developed, namely Σ-∆ programmable delay-line based comparator utilizing natural filtering of delay cells and on-time control logic. The controller is implemented both on FPGA and a 0.18-µm CMOS application specific IC. Experimental results obtained with a 1 W, 9 V, four-output buck prototype and IC simulations successfully verify controller operation.

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