Multimode digital SMPS controller IC for low-power management

Abstract

This paper introduces a novel low-power digital future, are expected to run at frequencies beyond 10 MHz. In controller for high frequency dc-dc switch-mode power supplies addition, the demonstrated systems do not offer a digital (SNIPS) that is well-suited for integration in power management solution for pulse-frequency modulation (PFM), which at light systems of small handheld devices. The controller operates at loads largely improves SMPS efficiency [3]. programmable constant switching frequencies up to 20 MHz and In this paper we present a new low-power architecture that can change mode of operation to improve the overall SNIPS allows integration of digitally controlled SMPS in the existing efficiency. The key elements of the controller are a high and upcoming handheld devices. The controller, shown in frequency digital pulse-width modulator (DPWM), based on a . . . a segmented ring oscillator, and a signal-race based digital pulseFig. , operates at programmable switchMg frequencies up to frequency modulator (DPFM). The controller is implemented in 20 MHz and can switch between PWM and PFM voltage a standard CMOS 0.18 ,Im process and its operation verified regulationmodes. both through simulations and experiments.

ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

“…The architecture presented in [79], also resembles the DPWM architecture based on a ring oscillator, with a difference in the size of the structure. The architecture of Figure 6g The main advantage of segmenting delay cells DPWM is that it can be realized with much smaller area than the delay-lined DPWM.…”

Digitally controlled low-power DC-DC converter with segmented output stage and gate charge based instantaneous efficiency optimization

“…This hybrid approach results in more power and area efficient implementation of the controller. It has been shown in previous publications [9][10][11][13][14] that all the digital blocks in controller of Fig.1 can be implemented on chip with low power consumption and small area. The architecture shown in Fig.1 has been modified to allow implementation of efficiency optimization techniques based on segmentation and gate-voltage swing scaling.…”

“…The dominant sources of losses in high frequency SMPS are gate-drive and conduction losses associated with power MOSFETs [1][2][11][12][13]. The conduction loss can be described with the following equation [2,7] …”

Design of low-power high-frequency digital controlled DC-DC switching power converter

“…It generates the output pulse duty cycle corresponding to a digital value. Several good methods have been proposed in the literature to design a high resolution DPWM module in the digital controller with moderate ADC resolution and high switching frequency, such as digital dither [10] , delay-line [5] , hybrid-DPWM [12] , and segmented-ring DPWM [13] . In this paper, a 10-bit resolution N DPWM is adopted, of which 8-bit is achieved by system clock count-comparator and 2-bit is obtained by digital dither.…”