This paper presents the first silicon-proven implementation of a lattice reduction (LR) algorithm, which achieves maximum likelihood diversity. The implementation is based on a novel hardware-optimized due to the Lenstra, Lenstra, and Lovász (LLL) algorithm, which significantly reduces its complexity by replacing all the computationally intensive LLL operations (multiplication, division, and square root) with low-complexity additions and comparisons. The proposed VLSI design utilizes a pipelined architecture that produces an LR-reduced matrix set every 40 cycles, which is a 60% reduction compared to current state-of-the-art LR field-programmable gate array implementations. The 0.13-µm CMOS LR core presented in this paper achieves a clock rate of 352 MHz, and thus is capable of sustaining a throughput of 880 Mb/s for 64-QAM multipleinput-multiple-output detection with superior performance while dissipating 59.4 mW at 1.32 V supply.Index Terms-Application-specific integrated circuit (ASIC) design, due to Lenstra, Lenstra, and Lovász (LLL) algorithm, lattice reduction, multiple-input-multiple-output (MIMO) detection, Seysen's algorithm.
This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. This reduction is achieved by replacing all the computationally intensive CLLL operations (multiplication, division and square root) with low-complexity additions and comparisons. The VLSI implementation uses a pipelined architecture that produces an LR-reduced matrix every 40 cycles, which is a 60% reduction compared to current implementations. The proposed design was synthesized in both 130μm and 65nm CMOS resulting in clock speeds of 332MHz and 833MHz, respectively. The 65nm result is a 4X improvement over the fastest LR implementation to date. The proposed LR implementation is able to sustain a throughput of 2Gbps, thus achieving the high data rates required by future standards such as IEEE 802.16m (WiMAX) and LTE-Advanced. I. INTRODUCTIONRecently, lattice-reduction (LR) has been proposed in conjunction with MIMO detection schemes to improve their performance via transforming the system model into an equivalent one with a more orthogonal channel matrix, thereby lowering the likelihood of detection errors due to noise perturbations [1]. The LLL algorithm (due to Lenstra, Lenstra and Lovasz) [2] is the most commonly used LR method and has been shown to achieve ML diversity for lowcomplexity detectors [3] and significantly improve the performance of more complex detectors such as K-Best [4]. A more efficient, complex-valued extension to LLL (known as CLLL) was developped in [5]. However, the VLSI implementation of CLLL remains problematic due to its computationally intensive operations and its nondeterministic complexity.Currently, only a small number VLSI implementations of LR have been reported in the literature, such as [6], [7] and [8]. Each of these designs were implemented on an FPGA platform. The Clarkson algorithm (CA), presented in [8], is a variant of CLLL that achieves a lower complexity by modifying the CLLL reduction criterion. However, CA, like CLLL, has the drawback of variable complexity and it also relies on computionally intensive operations such as division and multiplication. Another complex LR algorithm known as Seysen's algorithm (SA) was presented in [9], however, we show that SA has a much higher computational complexity than both CA and CLLL. Thus, SA is even more problematic from an implementation point of view. Therefore to achieve an efficient and high-throughput VLSI implementation of LR, there is a need for an algorithm with significantly reduced and deterministic complexity.In this paper we propose the design and ASIC implementation of a modified CLLL algorithm which achieves a 70% reduction in complexity over existing LR algorithms (including CLLL [5], CA [8], and SA [9]) with effectively the same BER performance. Our algorithm, which we named HOLLL (Hardware-Optimized LLL), eliminates the need for all computationally intensive LLL oper...
Lattice Reduction (LR) has been proposed as a method to enhance the performance of MIMO detectors such as ZF, MMSE and V-BLAST. Until recently, the application of LR to the superior K-Best tree-search detection algorithm was not practical due to the significant increase in complexity of K-Best as a result of the distortion of tree symmetry caused by LR. However, in our recently published work we developed an innovative K-Best algorithm to accommodate tree-asymmetry with no additional complexity. In this work, we build on this result and perform a detailed analysis of the effect of various LR algorithms on the performance of LR-aided K-Best. We show that LLL and Seysen provide equivalent performance enhancement, however, LLL displays a lower computational complexity and thus is more suitable for LR-aided K-Best. In this work we also show that the application of LR to K-Best allows a large reduction of the K value while maintaining its near-ML performance. For 64-QAM MIMO detection, this leads to about 70% reduction in the complexity of the K-Best detector.
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