Pseudo-resistor circuits are used to mimic large value resistors and base their success on the reduction of occupied areas with respect to physical devices of equal value. This article presents an optimized architecture of pseudo-resistor, made in standard CMOS 0.35 µm technology to bias a low-noise transimpedance amplifier for high-sensitivity applications in the frequency range 100 kHz-10 MHz. The architecture was selected after a critical review of the different topologies to implement high-value resistances with MOSFET transistors, considering their performance in terms of linearity of response, symmetric dynamic range, frequency behavior, and simplicity of realization. The resulting circuit consumes an area of 0.017 mm 2 and features a tunable resistance from 20 M to 20 G, dynamic offset reduction due to a more than linear I-V curve, and a high-frequency noise well below the one of a physical resistor of equal value. This latter aspect highlights the larger perspective of pseudo-resistors as building blocks in very low-noise applications in addition to the advantage in occupied areas they provide.

A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback (PCF) around the second stage introduces a left half plane (LHP) zero which cancels the phase shift introduced by the non-dominant pole, considerably. The dominant pole is at the output node which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method.The proposed amplifier is designed in a 0.18um CMOS process. It consumes 0.86mW power from a 1.8V power supply and occupies 3038.5µm 2 of chip area. The DC gain is 82.7dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5pF capacitive load. Also low frequency CMRR and PSRR + are 127dB and 83.2dB, respectively. They are 24.8dB and 24.2dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, Simulations show convenient performance of the circuit in process corners and also presence of mismatch.

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A power efficient, battery powered optogenetic headstage for doing in-vivo experiments with freely moving genetically modified animals is presented. The proposed system is designed with commercial off-the-shelf components, and is based on a Bluetooth Low Energy (BLE) System-on-Chip (SoC) with an integrated antenna and a programmable ARM Cortex-M3 microprocessor core able to control the circuit. The optical signal is generated using a compact laser diode (LD) suitable for a wearable headstage. LD produces light in a highly concentrated way considerably improving the LD-optical fiber coupling efficiency. The proposed optogenetic system is shown to provide 120 mW/mm 2 at the fiber tip with a current consumption of 60mA, considerably lower than LED-based systems. The system is remotely controlled by a smartphone app where the user can define optical stimulations patterns settings (optical power, frequency, duty cycle, etc.). It is also powerful enough to be ready to house additional optogenetics functionalities, like electrochemical sensing of the cell response, without significant modifications, thus being the basis of an integrated optogenetic platform.

We report the design in CMOS technology and the experimental characterization of an analog spiking neural network with on-chip unsupervised learning. Long-term synaptic memory is implemented using a floating-gate device in a standard 150 nm CMOS process. The neurons are operated with a voltage supply of only 0.4V, allowing an extremely low power dissipation with an energy dissipation per synaptic operation of about 55 fJ. The CMOS chip includes the circuits for implementing real-time learning of the network based on the Spike Time Dependent Plasticity algorithm. During the learning, the neurons produce pulses of ±4.5 V that change the synaptic weight by activating tunneling currents to change the charge in the floating gates.