High gain two‐stage amplifier with positive capacitive feedback compensation

Abstract

A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback (PCF) around the second stage introduces a left half plane (LHP) zero which cancels the phase shift introduced by the non-dominant pole, considerably. The dominant pole is at the output node which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method.The proposed amplifier is designed in a 0.18um CMOS process. It consumes 0.86mW power from a 1.8V power supply and occupies 3038.5µm 2 of chip area. The DC gain is 82.7dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5pF capacitive load. Also low frequency CMRR and PSRR + are 127dB and 83.2dB, respectively. They are 24.8dB and 24.2dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, Simulations show convenient performance of the circuit in process corners and also presence of mismatch.

Design and Analysis of High Gain Low Power CMOS Comparator

“…Main features of high speed, medium to high gain and stability with large loads are found in single-stage amplifiers. However, reduction of power supply voltage and intrinsic gain of transistor often traded for gain and output swing in single-stage amplifiers [8]. Several topologies have been introduced to improve gain and output swing in a single-stage amplifier such as a two-stage, folded cascade and telescopic [9]- [11].…”

“…4, December 2018: 471 -476 472 stage amplifier is often implemented to achieve higher gain as it provides higher output swing in the second stage [9]. It also provides better CMRR, lower power consumption and slew rate [8], [12]. However, it requires frequency compensation for stability in closed loop application where this amplifier has multiple zeros and poles [8], [11], [12].…”

“…It also provides better CMRR, lower power consumption and slew rate [8], [12]. However, it requires frequency compensation for stability in closed loop application where this amplifier has multiple zeros and poles [8], [11], [12]. Folded cascade amplifier has an advantage in providing a better power supply rejection ratio (PSRR), high speed and extensive frequency response.…”

High speed, open loop residue amplifier with linearity improvement

“…The OSC Opamp is a fully differential one, with PMOS input devices. The differential active load has been used in numerous applications in the past and recently in [19]. M L and M R are used to apply the input offset voltage of Opamp2, and Sw4 and Sw5 connect them to the Opamp's output.…”

“…The OSC method is already presented in Section 2.3, and performance of the proposed circuits in the presence of a mismatch is investigated in this section. Modelling and simulation of mismatch are done similar to [19], with the only difference that 0.35 μm process parameters are used in this work. Fig.…”