Inthispaper, a novel grid connected photovoltaic system is proposed which can function as an Active Power Filter (APF) with Maximum Power Point Tracking (MPPT). Filter reference current is derived using Fourier Transform. Considering 33% reduction in inverter switche s, cost of the gridconnect photovoltaic power plant can be reduced considerably. Using this approach, it is also possible to compensate for reactive and harmonic components of the local loads; moreover it can inject generated active power into grid at maximum power point of the photovoltaic cells. According to this, during daytime, the proposed system injects active power to the grid and at the same time compensates for the reactive power of the load. When there is no sunlight, the inverter only compensates local loads. Considering cost reduction, such capabilities may result in more application of the grid connected photovoltaic systems. Main novelty of the proposed system is simultaneous APF and MPPT functioning using single DC/AC converter. In fact, extra DC-DC converter is not required in the proposed system for MPPT. In order to verify the performance of the proposed method, some simulation is done using MATLAB/Simulink software. Also, some experimental results are presented for practical verification of the proposed grid connected inverter.
In this article, the design procedure for high-speed 5-2 and 6-2 compressors, along with their analysis, has been discussed. With the help of the combinational logic consisting of the 4-2 compressor and 3-2 counter blocks, a high-performance structure for 6-2 compressor has been achieved, which shows significant speed improvement over previous architectures. The optimization has been carried out by reducing the carry rippling issue between the adjacent compressor structures. Also, the help of some modifications, the proposed 6-2 compressor will turn into a 5-2 compressor where the latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The corresponding latencies of the proposed 5-2 and 6-2 structures are equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and the transistor count of proposed circuits are have remained at a moderate level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of the previously reported schemes.
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