The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packetbased communication [l]. We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summarypresmts the low cost, high performance on-chip communication network, called Spidergon, developed by the AST fidvanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.The main driving factor of the Spidergon research activity is to explore the complex design space to match a low cost hardware implementation. On that respect we performed the strategic choice of adopting a particular and fixed topology, to exploit the relevant properties for proposing an optimized NoC (Network on Chip) solution. Spidergon NoC is based on a novel scalable, regular, point-to-point topology. The Spidergon network connects a generic even number of nodes N=2n (n=2,3 ... ) as a hidirectional ring in both clockwise, and antklockwise directions uith in addition a cross connection for each couple of nodes. By a formal definition, each node i, with 05 i
The increasing complexity, in terms of both physical dimension and performance demand, of current Systems on Chip (SoCs) led to the development of new suitable interconnect architecture, leveraging on computer network technology, called Network on Chip (NoC). This paper describes two architectures of advanced physical link for NoC, the former based on mesochronous technology, the latter based on asynchronous
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