A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital 16 modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-m CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than 59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm 2 .
A single-chip 2x2 MIMO 802.11 b/g/n compliant WLAN AP/Router system-on-a chip(AP/Router SOC) that integrates all RF, analog, digital PHY, MAC, CPU and 5-port Ethernet functions as well as all necessary peripheral blocks has been integrated in 55nm CMOS. To reduce rBOM and PCB design complexity, two high power CMOS PAs, LNAs, and T/R switches are integrated for the MIMO transceiver. The radio transmits 22.4 dBm CCK mask compliant power and delivers 19dBm with EVM= -30dB at HT20 and 18dBm with EVM= -30dB at HT40. CCK RX sensitivity at the shared antenna port is -99dBm at 1Mbps rate, while CCK RX sensitivity is -100dBm at the auxiliary LNA path.
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