A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

Jerng, Albert; Sodini, C.G.

doi:10.1109/jssc.2007.900255

Cited by 146 publications

(101 citation statements)

References 19 publications

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“…The non-linearities in the DAC are one of the critical bottlenecks for the overall performance of the ADC. In order to cope with these non-linearities, various dynamic element matching (DEM) techniques have been used, for example, [76][77][78][79][80][81][82][83][84][85][86][87][88][89]. A disadvantage of the DEM is that size and power consumption grow exponentially with the increased word length and higher resolution of the digital feedback signal.…”

Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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“…Moreover the LO buffers used in that work to drive the large capacitance due to gate capacitance and wiring, is reported to consume about 12mA on each I and This problem can be addressed by either using a fewer number of unit elements by employing Σ∆ modulator before RFDAC to reduce the number of bits [10], or using discrete-oscillatory signal [11].…”

Section: Multimode Transmitter Using Direct-digital-to-rf Modulator [2]mentioning

confidence: 99%

On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters

Sadeghifar¹

2015

Linköping Studies in Science and Technology. Thesis

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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatorypulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have highenergy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency upconversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element.In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatorypulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work.Σ∆ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal's number of bits, still maintain the same resolution. By utilizing the Σ∆ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing Σ∆ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the Σ∆ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement.Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with Σ∆ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only t...

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“…This APS is Σ∆ modulator which converts input value x into the pulse train px. The mean value of the pulse density p x is proportional to x in time interval T [33], [42].…”

Section: B Sigma Delta Adcmentioning

confidence: 99%

“…Each segment is bordered by the local peaks in the INL(k) function. The deviations of the smoothed INL shape at both ends of FSR are caused by the error sources not involved in the error model (33). Table 3.…”

Section: B Experimental Verificationmentioning

confidence: 99%

Error Models of the Analog to Digital Converters

Michaeli¹,

Šaliga

2014

Measurement Science Review

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Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by the nonlinearities as a function of the output code. Progress in the microelectronics and missing information about circuital details together with the lack of knowledge about interfering effects caused by ADC installation prefers another modeling approach based on the input-output behavioral characterization by the input-output error box. Internal links in the ADC structure cause that the input-output error function could be described in a concise form by suitable function. Modeled functional parameters allow determining the integral error parameters of ADC. Paper is a survey of error models starting from the structural models for the most common architectures and their linkage with the behavioral models represented by the simple look up table or the functional description of nonlinear errors for the output codes.

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A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

Cited by 146 publications

References 19 publications

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Complexity and Power Reduction in Digital Delta-Sigma Modulators

On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters

Error Models of the Analog to Digital Converters

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