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This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed. 2D NAND Cell ScalingStructure Fig. 1 shows cross sections of a wrap FG cell and a planar FG cell. The increase of aspect ratio (A.R.) is a key limiter for the wrap FG cell scaling (Fig. 2). A.R. becomes >10 for both the word-line and the bit-line directions in a sub-20nm wrap cell. The planar cell eliminates this limitation [1].

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We report the impact of tunnel oxide nitridation (TON) on the evolution of random telegraph signal (RTS) and quick electron detrapping (QED) and investigate their microscopic origin. Applying nitridation at the SiO 2 /Si interface increases both Fermi level (RTS) and general midgap (QED) defects in fresh devices. However, it slows down additional defect generation and demonstrates improvement after severe program/erase cycling. Results from low-frequency 1/f noise indicate that TON aggravates RTS for high energy defects but hardens low energy defects, resulting in improved postcycled RTS. The suggestive defect chemistry is that strong Si-N bonding replaces relatively stable (but distorted) Si-O bonding, rather than passivating high energy dangling bonds. The Si-N bonding also causes more interface bonds to break, reducing strain and improving immunity against Fowler-Nordheim stress.Index Terms-Defect chemistry, Flash memory, low-frequency (LF) 1/f noise, multilevel cell (MLC), nitridation, oxynitride, quick electron detrapping (QED), random telegraph signal (RTS), tunnel oxide.

Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 Gb/mm2 with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling enabled the density scaling. Logical scaling has been successfully realized, too. TLC (triple-level cell, 3 bits per cell) is now the mainstream in 3D NAND, while QLC (quad-level cell, 4 bits per cell) is increasing the presence. Several attempts and partial demonstrations were made for PLC (penta-level cell, 5 bits per cell). CMOS under array (CuA) enabled the die size reduction and performance improvements. Program and erase schemes to address the technology challenges such as short-term data retention of the charge-trap cell and the large block size are being investigated.

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